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Thu, 24 Mar 2016 13:25:34 +0900 (KST) From: Chanwoo Choi To: myungjoo.ham@samsung.com, kyungmin.park@samsung.com, k.kozlowski@samsung.com, kgene@kernel.org Subject: [PATCH v5 17/21] ARM: dts: Add bus nodes using VDD_MIF for Exynos4210 Date: Thu, 24 Mar 2016 13:25:26 +0900 Message-id: <1458793530-31897-18-git-send-email-cw00.choi@samsung.com> X-Mailer: git-send-email 1.8.0 In-reply-to: <1458793530-31897-1-git-send-email-cw00.choi@samsung.com> References: <1458793530-31897-1-git-send-email-cw00.choi@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrPIsWRmVeSWpSXmKPExsWyRsSkUNc+53OYwefNjBbXvzxntZh/5Byr Rf+bhawW516tZLR4/cLQov/xa2aLs01v2C02Pb7GanF51xw2i8+9RxgtZpzfx2SxbuMtdovb l3ktll6/yGRxu3EFm8WE6WtZLM6cvsRq0br3CLtF2+oPrA7CHmvmrWH0aGnuYfO43NfL5LFz 1l12j5XLv7B5bFrVyeaxeUm9x79j7B5brrazePRtWcXo8XmTXAB3FJdNSmpOZllqkb5dAldG 1wrhgl0qFd8vKTUwPpfpYuTkkBAwkfj4/wQrhC0mceHeerYuRi4OIYEVjBKbV01ghSna3HGd GSKxlFGi9fxSsISQwBdGiQl/WEBsNgEtif0vbrCB2CICKRKPH54Em8QsMIVZYvn0ZqAiDg5h AT+JQ0fVQGpYBFQljl+9CdbLK+Am8fzrVTaIZXISH/Y8YgexOYHiUxuaWCB2uUo8fbyJFWSm hMBMDonOV3/ZIQYJSHybfAhsvoSArMSmA8wQcyQlDq64wTKBUXgBI8MqRtHUguSC4qT0IiO9 4sTc4tK8dL3k/NxNjMB4PP3vWd8OxpsHrA8xCnAwKvHwNnB8DhNiTSwrrsw9xGgKtGEis5Ro cj4w6vNK4g2NzYwsTE1MjY3MLc2UxHkTpH4GCwmkJ5akZqemFqQWxReV5qQWH2Jk4uCUamAM 3H7TKNowvaTjydR5v46rrU2vFjq1eRb/v2sWQcH1CqvXTFl/y+jYlT1p+VeubssIeFdrsouh J7EyPaiX099Fq2RV2v9zQlN1M7t2pO7/8fTgsnMyaRma8/oLFims115bn+d+8vgpgYyp625E ZnLPsJ0/yaZtFkdyyRSTa0uOFX/4cv3tc45+JZbijERDLeai4kQAz6oTGcICAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrDIsWRmVeSWpSXmKPExsVy+t9jAV27nM9hBk3fzS2uf3nOajH/yDlW i/43C1ktzr1ayWjx+oWhRf/j18wWZ5vesFtsenyN1eLyrjlsFp97jzBazDi/j8li3cZb7Ba3 L/NaLL1+kcniduMKNosJ09eyWJw5fYnVonXvEXaLttUfWB2EPdbMW8Po0dLcw+Zxua+XyWPn rLvsHiuXf2Hz2LSqk81j85J6j3/H2D22XG1n8ejbsorR4/MmuQDuqAZGm4zUxJTUIoXUvOT8 lMy8dFsl7+B453hTMwNDXUNLC3MlhbzE3FRbJRefAF23zByg75QUyhJzSoFCAYnFxUr6dpgm hIa46VrANEbo+oYEwfUYGaCBhDWMGV0rhAt2qVR8v6TUwPhcpouRk0NCwERic8d1ZghbTOLC vfVsXYxcHEICSxklWs8vZQVJCAl8YZSY8IcFxGYT0JLY/+IGG4gtIpAi8fjhSbAGZoEpzBLL pzcDFXFwCAv4SRw6qgZSwyKgKnH86k2wXl4BN4nnX6+yQSyTk/iw5xE7iM0JFJ/a0MQCsctV 4unjTawTGHkXMDKsYpRILUguKE5KzzXMSy3XK07MLS7NS9dLzs/dxAiO+WdSOxgP7nI/xCjA wajEw3uD63OYEGtiWXFl7iFGCQ5mJRHe9eFAId6UxMqq1KL8+KLSnNTiQ4ymQIdNZJYSTc4H pqO8knhDYxMzI0sjc0MLI2NzJXHex//XhQkJpCeWpGanphakFsH0MXFwSjUwxpienCi7Y+P1 jd7i/Qudvpfdcrjswn5i3+L2a//yVHa1vimtnvxojljP1Mnq0Vci2OU+PNF9p3fwe4a5ALfy 0neHQ68JT/BY/qWy1GNK0M70p0deKx5YeIS1OW3qflb5CvEFD6akrHy7saMkz/5mNtOLuaEt zwNiSv8IVnS93fqyvUfS3dX/sRJLcUaioRZzUXEiAL+3CTQPAwAA DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160323_212608_830906_E655DCC7 X-CRM114-Status: GOOD ( 10.42 ) X-Spam-Score: -6.9 (------) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux@arm.linux.org.uk, cw00.choi@samsung.com, pawel.moll@arm.com, ijc+devicetree@hellion.org.uk, linux.amoon@gmail.com, linux-pm@vger.kernel.org, rjw@rjwysocki.net, linux-kernel@vger.kernel.org, tjakobi@math.uni-bielefeld.de, robh+dt@kernel.org, galak@codeaurora.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds the bus nodes for Exynos4210 SoC. Exynos4210 SoC has one power line for all buses to translate data between DRAM and sub-blocks. Following list specifies the detailed relation between DRAM and sub-blocks: - DMC/ACP clock for DMC (Dynamic Memory Controller) - ACLK200 clock for LCD0 - ACLK100 clock for PERIL/PERIR/MFC(PCLK) - ACLK160 clock for CAM/TV/LCD0/LCD1 - ACLK133 clock for FSYS/GPS - GDL/GDR clock for LEFTBUS/RIGHTBUS - SCLK_MFC clock for MFC Signed-off-by: Chanwoo Choi Reviewed-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos4210.dtsi | 159 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 159 insertions(+) diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi index c1cb8df6da07..2d9b02967105 100644 --- a/arch/arm/boot/dts/exynos4210.dtsi +++ b/arch/arm/boot/dts/exynos4210.dtsi @@ -257,6 +257,165 @@ power-domains = <&pd_lcd1>; #iommu-cells = <0>; }; + + bus_dmc: bus_dmc { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DIV_DMC>; + clock-names = "bus"; + operating-points-v2 = <&bus_dmc_opp_table>; + status = "disabled"; + }; + + bus_acp: bus_acp { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DIV_ACP>; + clock-names = "bus"; + operating-points-v2 = <&bus_acp_opp_table>; + status = "disabled"; + }; + + bus_peri: bus_peri { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_ACLK100>; + clock-names = "bus"; + operating-points-v2 = <&bus_peri_opp_table>; + status = "disabled"; + }; + + bus_fsys: bus_fsys { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_ACLK133>; + clock-names = "bus"; + operating-points-v2 = <&bus_fsys_opp_table>; + status = "disabled"; + }; + + bus_display: bus_display { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_ACLK160>; + clock-names = "bus"; + operating-points-v2 = <&bus_display_opp_table>; + status = "disabled"; + }; + + bus_lcd0: bus_lcd0 { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_ACLK200>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_leftbus: bus_leftbus { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DIV_GDL>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_rightbus: bus_rightbus { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DIV_GDR>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_mfc: bus_mfc { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_SCLK_MFC>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_dmc_opp_table: opp_table1 { + compatible = "operating-points-v2"; + opp-shared; + + opp@134000000 { + opp-hz = /bits/ 64 <134000000>; + opp-microvolt = <1025000>; + }; + opp@267000000 { + opp-hz = /bits/ 64 <267000000>; + opp-microvolt = <1050000>; + }; + opp@400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <1150000>; + }; + }; + + bus_acp_opp_table: opp_table2 { + compatible = "operating-points-v2"; + opp-shared; + + opp@134000000 { + opp-hz = /bits/ 64 <134000000>; + }; + opp@160000000 { + opp-hz = /bits/ 64 <160000000>; + }; + opp@200000000 { + opp-hz = /bits/ 64 <200000000>; + }; + }; + + bus_peri_opp_table: opp_table3 { + compatible = "operating-points-v2"; + opp-shared; + + opp@5000000 { + opp-hz = /bits/ 64 <5000000>; + }; + opp@100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + }; + + bus_fsys_opp_table: opp_table4 { + compatible = "operating-points-v2"; + opp-shared; + + opp@10000000 { + opp-hz = /bits/ 64 <10000000>; + }; + opp@134000000 { + opp-hz = /bits/ 64 <134000000>; + }; + }; + + bus_display_opp_table: opp_table5 { + compatible = "operating-points-v2"; + opp-shared; + + opp@100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + opp@134000000 { + opp-hz = /bits/ 64 <134000000>; + }; + opp@160000000 { + opp-hz = /bits/ 64 <160000000>; + }; + }; + + bus_leftbus_opp_table: opp_table6 { + compatible = "operating-points-v2"; + opp-shared; + + opp@100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + opp@160000000 { + opp-hz = /bits/ 64 <160000000>; + }; + opp@200000000 { + opp-hz = /bits/ 64 <200000000>; + }; + }; }; &gic {