| Message ID | 1458838215-23314-13-git-send-email-narmstrong@baylibre.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Thu, Mar 24, 2016 at 05:50:09PM +0100, Neil Armstrong wrote: > Add pinctrl and gpio DT bindings for PLX Technology OXNAS SoC Family. > This version supports the ARM926EJ-S based OX810SE SoC with 34 IO pins. > > Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> > --- > .../devicetree/bindings/gpio/gpio_oxnas.txt | 47 ++++++++++++++++++ > .../bindings/pinctrl/plxtech,pinctrl.txt | 57 ++++++++++++++++++++++ > 2 files changed, 104 insertions(+) > create mode 100644 Documentation/devicetree/bindings/gpio/gpio_oxnas.txt > create mode 100644 Documentation/devicetree/bindings/pinctrl/plxtech,pinctrl.txt > > diff --git a/Documentation/devicetree/bindings/gpio/gpio_oxnas.txt b/Documentation/devicetree/bindings/gpio/gpio_oxnas.txt > new file mode 100644 > index 0000000..4530fa9 > --- /dev/null > +++ b/Documentation/devicetree/bindings/gpio/gpio_oxnas.txt > @@ -0,0 +1,47 @@ > +* PLX Technology OXNAS SoC GPIO Controller > + > +Required properties: > + - compatible: "oxsemi,ox810se-gpio" > + - reg: Base address and length for the device. > + - interrupts: The port interrupt shared by all pins. > + - gpio-controller: Marks the port as GPIO controller. > + - #gpio-cells: Two. The first cell is the pin number and > + the second cell is used to specify the gpio polarity as defined in > + defined in <dt-bindings/gpio/gpio.h>: > + 0 = GPIO_ACTIVE_HIGH > + 1 = GPIO_ACTIVE_LOW > + - interrupt-controller: Marks the device node as an interrupt controller. > + - #interrupt-cells: Two. The first cell is the GPIO number and second cell > + is used to specify the trigger type as defined in > + <dt-bindings/interrupt-controller/irq.h>: > + IRQ_TYPE_EDGE_RISING > + IRQ_TYPE_EDGE_FALLING > + IRQ_TYPE_EDGE_BOTH > + - plxtech,gpio-bank: Specifies which bank a controller owns. How is this used? > + - gpio-ranges: Interaction with the PINCTRL subsystem. > + - ngpios: Specifies the gpio lines count in this specific bank. > + > +Example: > + > +gpio0: gpio@0 { > + compatible = "oxsemi,ox810se-gpio"; > + reg = <0x000000 0x100000>; > + interrupts = <21>; > + #gpio-cells = <2>; > + gpio-controller; > + interrupt-controller; > + #interrupt-cells = <2>; > + plxtech,gpio-bank = <0>; > + gpio-ranges = <&pinctrl 0 0 32>; > + ngpios = <32>; Is 32 the max? It should not be needed then. > +}; > + > +keys { > + ... > + > + button@sw1 { sw1 is not a unit-address. Just do "sw1-button". > + label = "ESC"; > + linux,code = <1>; > + gpios = <&gpio0 12 0>; > + }; > +};
On Thu, Mar 24, 2016 at 5:50 PM, Neil Armstrong <narmstrong@baylibre.com> wrote: > Add pinctrl and gpio DT bindings for PLX Technology OXNAS SoC Family. > This version supports the ARM926EJ-S based OX810SE SoC with 34 IO pins. > > Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> (...) > + - plxtech,gpio-bank: Specifies which bank a controller owns. Rob commented on this too. Other drivers just use "gpio-bank" for this, so use that. I should add it to the generic bindings document. Yours, Linus Walleij
On Fri, Mar 25, 2016 at 3:48 PM, Rob Herring <robh@kernel.org> wrote: > On Thu, Mar 24, 2016 at 05:50:09PM +0100, Neil Armstrong wrote: >> Add pinctrl and gpio DT bindings for PLX Technology OXNAS SoC Family. >> This version supports the ARM926EJ-S based OX810SE SoC with 34 IO pins. >> >> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> >> + - plxtech,gpio-bank: Specifies which bank a controller owns. > > How is this used? That is used to give a unique ID number to the bank. Hardware often need this to cross-reference pin controllers to GPIO banks. I should add it as "gpio-bank" to the generic bindings instead, several platforms already use this and there is no point in having a vendor prefix in front of it. Yours, Linus Walleij
On Thu, Mar 31, 2016 at 3:58 AM, Linus Walleij <linus.walleij@linaro.org> wrote: > On Fri, Mar 25, 2016 at 3:48 PM, Rob Herring <robh@kernel.org> wrote: >> On Thu, Mar 24, 2016 at 05:50:09PM +0100, Neil Armstrong wrote: >>> Add pinctrl and gpio DT bindings for PLX Technology OXNAS SoC Family. >>> This version supports the ARM926EJ-S based OX810SE SoC with 34 IO pins. >>> >>> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> > >>> + - plxtech,gpio-bank: Specifies which bank a controller owns. >> >> How is this used? > > That is used to give a unique ID number to the bank. > > Hardware often need this to cross-reference pin controllers > to GPIO banks. > > I should add it as "gpio-bank" to the generic bindings > instead, several platforms already use this and there is > no point in having a vendor prefix in front of it. Okay, now it is clearer. I don't want this documented as a common property because I don't want to encourage it's use. I only see 2 users currently: ST and PIC32. Looking at one example, it appears to be redundant already. nomadik-gpio-chips property already gives you the index. The index of the phandles is the bank numbering. PIC32 could do the same. Rob
On 03/31/2016 03:36 PM, Rob Herring wrote: > On Thu, Mar 31, 2016 at 3:58 AM, Linus Walleij <linus.walleij@linaro.org> wrote: >> On Fri, Mar 25, 2016 at 3:48 PM, Rob Herring <robh@kernel.org> wrote: >>> On Thu, Mar 24, 2016 at 05:50:09PM +0100, Neil Armstrong wrote: >>>> Add pinctrl and gpio DT bindings for PLX Technology OXNAS SoC Family. >>>> This version supports the ARM926EJ-S based OX810SE SoC with 34 IO pins. >>>> >>>> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> >> >>>> + - plxtech,gpio-bank: Specifies which bank a controller owns. >>> >>> How is this used? >> >> That is used to give a unique ID number to the bank. >> >> Hardware often need this to cross-reference pin controllers >> to GPIO banks. >> >> I should add it as "gpio-bank" to the generic bindings >> instead, several platforms already use this and there is >> no point in having a vendor prefix in front of it. > > Okay, now it is clearer. I don't want this documented as a common > property because I don't want to encourage it's use. I only see 2 > users currently: ST and PIC32. > > Looking at one example, it appears to be redundant already. > nomadik-gpio-chips property already gives you the index. The index of > the phandles is the bank numbering. PIC32 could do the same. > > Rob > Hi, What should I use ? I need to repost in a separate patchset with vendor replaced by Oxford Semiconductor. Should I get rid of the vendor prefix of gpio-bank ? Neil
On Fri, Apr 1, 2016 at 9:30 AM, Neil Armstrong <narmstrong@baylibre.com> wrote: > On 03/31/2016 03:36 PM, Rob Herring wrote: >> On Thu, Mar 31, 2016 at 3:58 AM, Linus Walleij <linus.walleij@linaro.org> wrote: >>> On Fri, Mar 25, 2016 at 3:48 PM, Rob Herring <robh@kernel.org> wrote: >>>> On Thu, Mar 24, 2016 at 05:50:09PM +0100, Neil Armstrong wrote: >>>>> Add pinctrl and gpio DT bindings for PLX Technology OXNAS SoC Family. >>>>> This version supports the ARM926EJ-S based OX810SE SoC with 34 IO pins. >>>>> >>>>> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> >>> >>>>> + - plxtech,gpio-bank: Specifies which bank a controller owns. >>>> >>>> How is this used? >>> >>> That is used to give a unique ID number to the bank. >>> >>> Hardware often need this to cross-reference pin controllers >>> to GPIO banks. >>> >>> I should add it as "gpio-bank" to the generic bindings >>> instead, several platforms already use this and there is >>> no point in having a vendor prefix in front of it. >> >> Okay, now it is clearer. I don't want this documented as a common >> property because I don't want to encourage it's use. I only see 2 >> users currently: ST and PIC32. >> >> Looking at one example, it appears to be redundant already. >> nomadik-gpio-chips property already gives you the index. The index of >> the phandles is the bank numbering. PIC32 could do the same. >> >> Rob >> > > Hi, > > What should I use ? Maybe gpio-ranges as you asked. Not really sure as I haven't used it. > I need to repost in a separate patchset with vendor replaced by Oxford Semiconductor. > Should I get rid of the vendor prefix of gpio-bank ? No, because I think you should get rid of the property. Rob
On 04/01/2016 05:19 PM, Rob Herring wrote: > On Fri, Apr 1, 2016 at 9:30 AM, Neil Armstrong <narmstrong@baylibre.com> wrote: >>> >>> Rob >>> >> >> Hi, >> >> What should I use ? > > Maybe gpio-ranges as you asked. Not really sure as I haven't used it. If I use gpio-ranges I can get rid of gpio-bank and ngpios properties. > >> I need to repost in a separate patchset with vendor replaced by Oxford Semiconductor. >> Should I get rid of the vendor prefix of gpio-bank ? > > No, because I think you should get rid of the property. > > Rob > If gpio-ranges is OK, I can post it ASAP. Thanks, Neil
On Thu, Mar 31, 2016 at 3:36 PM, Rob Herring <robh@kernel.org> wrote: > Looking at one example, it appears to be redundant already. > nomadik-gpio-chips property already gives you the index. The index of > the phandles is the bank numbering. PIC32 could do the same. nomadik-gpio-chips is a property on the pin controller, so it goes the wrong direction I think, the pin controller knows these indexes but the GPIO chip does not know what index it has. Yours, Linus Walleij
On Fri, Apr 1, 2016 at 5:48 PM, Neil Armstrong <narmstrong@baylibre.com> wrote: > On 04/01/2016 05:19 PM, Rob Herring wrote: >> On Fri, Apr 1, 2016 at 9:30 AM, Neil Armstrong <narmstrong@baylibre.com> wrote: >>>> >>> What should I use ? >> >> Maybe gpio-ranges as you asked. Not really sure as I haven't used it. > > If I use gpio-ranges I can get rid of gpio-bank and ngpios properties. I'm not super-happy about that but I see that it can be used this way... hm. Yours, Linus Walleij
diff --git a/Documentation/devicetree/bindings/gpio/gpio_oxnas.txt b/Documentation/devicetree/bindings/gpio/gpio_oxnas.txt new file mode 100644 index 0000000..4530fa9 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/gpio_oxnas.txt @@ -0,0 +1,47 @@ +* PLX Technology OXNAS SoC GPIO Controller + +Required properties: + - compatible: "oxsemi,ox810se-gpio" + - reg: Base address and length for the device. + - interrupts: The port interrupt shared by all pins. + - gpio-controller: Marks the port as GPIO controller. + - #gpio-cells: Two. The first cell is the pin number and + the second cell is used to specify the gpio polarity as defined in + defined in <dt-bindings/gpio/gpio.h>: + 0 = GPIO_ACTIVE_HIGH + 1 = GPIO_ACTIVE_LOW + - interrupt-controller: Marks the device node as an interrupt controller. + - #interrupt-cells: Two. The first cell is the GPIO number and second cell + is used to specify the trigger type as defined in + <dt-bindings/interrupt-controller/irq.h>: + IRQ_TYPE_EDGE_RISING + IRQ_TYPE_EDGE_FALLING + IRQ_TYPE_EDGE_BOTH + - plxtech,gpio-bank: Specifies which bank a controller owns. + - gpio-ranges: Interaction with the PINCTRL subsystem. + - ngpios: Specifies the gpio lines count in this specific bank. + +Example: + +gpio0: gpio@0 { + compatible = "oxsemi,ox810se-gpio"; + reg = <0x000000 0x100000>; + interrupts = <21>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + plxtech,gpio-bank = <0>; + gpio-ranges = <&pinctrl 0 0 32>; + ngpios = <32>; +}; + +keys { + ... + + button@sw1 { + label = "ESC"; + linux,code = <1>; + gpios = <&gpio0 12 0>; + }; +}; diff --git a/Documentation/devicetree/bindings/pinctrl/plxtech,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/plxtech,pinctrl.txt new file mode 100644 index 0000000..dc4907b --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/plxtech,pinctrl.txt @@ -0,0 +1,57 @@ +* PLX Technology OXNAS SoC Family Pin Controller + +Please refer to pinctrl-bindings.txt, ../gpio/gpio.txt, and +../interrupt-controller/interrupts.txt for generic information regarding +pin controller, GPIO, and interrupt bindings. + +OXNAS 'pin configuration node' is a node of a group of pins which can be +used for a specific device or function. This node represents configurations of +pins, optional function, and optional mux related configuration. + +Required properties for pin controller node: + - compatible: "oxsemi,ox810se-pinctrl" + - plxtech,sys-ctrl: a phandle to the system controller syscon node + +Required properties for pin configuration sub-nodes: + - pins: List of pins to which the configuration applies. + +Optional properties for pin configuration sub-nodes: +---------------------------------------------------- + - function: Mux function for the specified pins. + - bias-pull-up: Enable weak pull-up. + +Example: + +pinctrl: pinctrl { + compatible = "oxsemi,ox810se-pinctrl"; + + /* Regmap for sys registers */ + plxtech,sys-ctrl = <&sys>; + + pinctrl_uart2: pinctrl_uart2 { + uart2a { + pins = "gpio31"; + function = "fct3"; + }; + uart2b { + pins = "gpio32"; + function = "fct3"; + }; + }; +}; + +uart2: serial@900000 { + compatible = "ns16550a"; + reg = <0x900000 0x100000>; + clocks = <&sysclk>; + interrupts = <29>; + reg-shift = <0>; + fifo-size = <16>; + reg-io-width = <1>; + current-speed = <115200>; + no-loopback-test; + status = "disabled"; + resets = <&reset 22>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; +};
Add pinctrl and gpio DT bindings for PLX Technology OXNAS SoC Family. This version supports the ARM926EJ-S based OX810SE SoC with 34 IO pins. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> --- .../devicetree/bindings/gpio/gpio_oxnas.txt | 47 ++++++++++++++++++ .../bindings/pinctrl/plxtech,pinctrl.txt | 57 ++++++++++++++++++++++ 2 files changed, 104 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/gpio_oxnas.txt create mode 100644 Documentation/devicetree/bindings/pinctrl/plxtech,pinctrl.txt