From patchwork Thu Mar 24 16:50:09 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 8662991 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 102C59F326 for ; Thu, 24 Mar 2016 16:57:12 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 1667C200E5 for ; Thu, 24 Mar 2016 16:57:11 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 29D80200DE for ; Thu, 24 Mar 2016 16:57:10 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1aj8XY-0007pu-Ci; Thu, 24 Mar 2016 16:55:20 +0000 Received: from mail-wm0-x233.google.com ([2a00:1450:400c:c09::233]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1aj8TU-00048x-Lm for linux-arm-kernel@lists.infradead.org; Thu, 24 Mar 2016 16:51:12 +0000 Received: by mail-wm0-x233.google.com with SMTP id l68so74921814wml.1 for ; Thu, 24 Mar 2016 09:50:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=qvQpsfC5p1MJSLg2fJkacMpcIT3Yk4TeiZC2AbUEOWY=; b=JAF0ULFoT8JG8JtRDAStb5Ay18KLuNtJBABUrhAzbqq3yOoJBJDHAob/W4xnCOAL4U re18zekG9oa13qQJ08H3xB8UqCa9PW/Op4FLe7pUQNvvdclVM151Q6kzdZFPSlLgWEPG BZROPrgSfQva4Y4JZ6XKS/qlT6F5smN3XFcA8U053iI8B6oxQ9xB7PgDbaXkQZAWYMMi UFoOa1opeQ3x+HDh0vSMX5Vn18Hy00Syj9ONcxmQ2+mi0AjfoHfROXJSVzgKjZ/AHB9N m88DLm4ZBCahDhqrh8Y2bWiXC/f6F7yLo4OHgUI9mZH1byB66G9hkUWn3s/6B7P4OphW dGiw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=qvQpsfC5p1MJSLg2fJkacMpcIT3Yk4TeiZC2AbUEOWY=; b=Cr/ZLpRv9y5L+Eu+QpvkVozIDKroOmu/N/qHpVzpqKq4NXLeHoV3b7Zu7yT4IvpB4G nI3upFEbZEhW1psAIdpW4lopmeKCjzdEUsT9R/AedB/06Xh/bvMKvtgaehfk6HZVKZ3b RjyfyWT4nTisUZLB5Z7ljs0AhYfWdhj0oDRUeQNFl11FF4XD2guU4Pqv4D4EhuLckxwM jAnigcFoiORtur3YVU2xJqvRirvrrmijG/FtsTFHsvhaH7bsQl+d4/s9fpNYv6tvy6V5 zzWRg/aNdpoceh6FYKDwE5KnRZZB0/D0sv437d6JCVpUdMHJ6OALM9tCl9fj0wQMa6pu 5pYw== X-Gm-Message-State: AD7BkJLdSh/ZWVkLyy/KSuNY0ZI7eJiUlbhv+PkTOyhXFv3rdO1SqB2zCs0Gcgn4nZeefTGt X-Received: by 10.28.226.212 with SMTP id z203mr35409988wmg.73.1458838251235; Thu, 24 Mar 2016 09:50:51 -0700 (PDT) Received: from localhost.localdomain ([90.63.244.31]) by smtp.gmail.com with ESMTPSA id lz5sm8177545wjb.5.2016.03.24.09.50.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 24 Mar 2016 09:50:50 -0700 (PDT) From: Neil Armstrong To: linux-kernel@vger.kernel.org, linux@arm.linux.org.uk, linux-arm-kernel@lists.infradead.org, linus.walleij@linaro.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v3 12/18] dt-bindings: Add PLX Technology OXNAS pinctrl and gpio bindings Date: Thu, 24 Mar 2016 17:50:09 +0100 Message-Id: <1458838215-23314-13-git-send-email-narmstrong@baylibre.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1458838215-23314-1-git-send-email-narmstrong@baylibre.com> References: <1458838215-23314-1-git-send-email-narmstrong@baylibre.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160324_095109_057578_58602192 X-CRM114-Status: GOOD ( 16.46 ) X-Spam-Score: -1.9 (-) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Neil Armstrong MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add pinctrl and gpio DT bindings for PLX Technology OXNAS SoC Family. This version supports the ARM926EJ-S based OX810SE SoC with 34 IO pins. Signed-off-by: Neil Armstrong --- .../devicetree/bindings/gpio/gpio_oxnas.txt | 47 ++++++++++++++++++ .../bindings/pinctrl/plxtech,pinctrl.txt | 57 ++++++++++++++++++++++ 2 files changed, 104 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/gpio_oxnas.txt create mode 100644 Documentation/devicetree/bindings/pinctrl/plxtech,pinctrl.txt diff --git a/Documentation/devicetree/bindings/gpio/gpio_oxnas.txt b/Documentation/devicetree/bindings/gpio/gpio_oxnas.txt new file mode 100644 index 0000000..4530fa9 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/gpio_oxnas.txt @@ -0,0 +1,47 @@ +* PLX Technology OXNAS SoC GPIO Controller + +Required properties: + - compatible: "oxsemi,ox810se-gpio" + - reg: Base address and length for the device. + - interrupts: The port interrupt shared by all pins. + - gpio-controller: Marks the port as GPIO controller. + - #gpio-cells: Two. The first cell is the pin number and + the second cell is used to specify the gpio polarity as defined in + defined in : + 0 = GPIO_ACTIVE_HIGH + 1 = GPIO_ACTIVE_LOW + - interrupt-controller: Marks the device node as an interrupt controller. + - #interrupt-cells: Two. The first cell is the GPIO number and second cell + is used to specify the trigger type as defined in + : + IRQ_TYPE_EDGE_RISING + IRQ_TYPE_EDGE_FALLING + IRQ_TYPE_EDGE_BOTH + - plxtech,gpio-bank: Specifies which bank a controller owns. + - gpio-ranges: Interaction with the PINCTRL subsystem. + - ngpios: Specifies the gpio lines count in this specific bank. + +Example: + +gpio0: gpio@0 { + compatible = "oxsemi,ox810se-gpio"; + reg = <0x000000 0x100000>; + interrupts = <21>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + plxtech,gpio-bank = <0>; + gpio-ranges = <&pinctrl 0 0 32>; + ngpios = <32>; +}; + +keys { + ... + + button@sw1 { + label = "ESC"; + linux,code = <1>; + gpios = <&gpio0 12 0>; + }; +}; diff --git a/Documentation/devicetree/bindings/pinctrl/plxtech,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/plxtech,pinctrl.txt new file mode 100644 index 0000000..dc4907b --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/plxtech,pinctrl.txt @@ -0,0 +1,57 @@ +* PLX Technology OXNAS SoC Family Pin Controller + +Please refer to pinctrl-bindings.txt, ../gpio/gpio.txt, and +../interrupt-controller/interrupts.txt for generic information regarding +pin controller, GPIO, and interrupt bindings. + +OXNAS 'pin configuration node' is a node of a group of pins which can be +used for a specific device or function. This node represents configurations of +pins, optional function, and optional mux related configuration. + +Required properties for pin controller node: + - compatible: "oxsemi,ox810se-pinctrl" + - plxtech,sys-ctrl: a phandle to the system controller syscon node + +Required properties for pin configuration sub-nodes: + - pins: List of pins to which the configuration applies. + +Optional properties for pin configuration sub-nodes: +---------------------------------------------------- + - function: Mux function for the specified pins. + - bias-pull-up: Enable weak pull-up. + +Example: + +pinctrl: pinctrl { + compatible = "oxsemi,ox810se-pinctrl"; + + /* Regmap for sys registers */ + plxtech,sys-ctrl = <&sys>; + + pinctrl_uart2: pinctrl_uart2 { + uart2a { + pins = "gpio31"; + function = "fct3"; + }; + uart2b { + pins = "gpio32"; + function = "fct3"; + }; + }; +}; + +uart2: serial@900000 { + compatible = "ns16550a"; + reg = <0x900000 0x100000>; + clocks = <&sysclk>; + interrupts = <29>; + reg-shift = <0>; + fifo-size = <16>; + reg-io-width = <1>; + current-speed = <115200>; + no-loopback-test; + status = "disabled"; + resets = <&reset 22>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; +};