From patchwork Thu Mar 24 16:49:58 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 8662801 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 21E839F3D1 for ; Thu, 24 Mar 2016 16:53:00 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 294F6200DE for ; Thu, 24 Mar 2016 16:52:59 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 25CEE200E5 for ; Thu, 24 Mar 2016 16:52:58 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1aj8Tk-0004M0-QO; Thu, 24 Mar 2016 16:51:24 +0000 Received: from mail-wm0-x22d.google.com ([2a00:1450:400c:c09::22d]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1aj8TN-00044j-JV for linux-arm-kernel@lists.infradead.org; Thu, 24 Mar 2016 16:51:03 +0000 Received: by mail-wm0-x22d.google.com with SMTP id l68so244838072wml.0 for ; Thu, 24 Mar 2016 09:50:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=jI3Vvz0d1tyP9mgBWiveKDTQ0mht2bbydOpHx/QqeZs=; b=SVM1XsRyNLGwBdC6fJ2pLJPfVGy1kC30uCJFPyqsFo5hr1kG22MZ7LkuoM56/QG1v4 UPcRN3QN1IkDnOmG7+CDySTbyqWuj5uu9NBityaOPgsu4Bmj1rrdfh1aEfSYCPz+61VM 8RhZEnCvB4Lgts58mr4FhuAybxIhZIWPIGIWEskhHMyp3djtXNqpviQ0c2+uQ1ekmZ6N 7pd+J/bWhgOttaotfXxUeJ4iUUDWbQNwShs3q5P0U46NXgcryZnSFYnxSVHCvB13UVvn AYvDU4CcR6Sa1nWjuX3CaPGjXVyrTxsEq5rokR814atTdNpJbv95tLlWCAvwGl6gpazJ iX/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=jI3Vvz0d1tyP9mgBWiveKDTQ0mht2bbydOpHx/QqeZs=; b=jYnK3nerTgKhs+NIrgOAtBLMmcwYmPiSlLHX0o2pzuCG4wvsk7mxdmIEFAwcmAVzio BtW5faP4Pm7/+rPrXZ5FYv+natpY2HvK+FjGBH7HsqiU0wSSmmW8fNYOavpsd2p30bqo iOjh9vLk+Q+8WwZvzvtU9yD3fAfk6jVuY1ya5e3rInxpIs7xcV+FLAT7HTLfBqdUhRsJ GE0xzfsI3hZSmmfPQPk9cInkfeBuoiQENB0NcZtO21JXLQEl0PUjDUS6wYRUzhDS7Q+W hNKVXsmyNAEXFOkq0eIkObyUZNOfBnrQtB39WYrSTu2oo4YSxo5WHdAxjoDm1EmN92iw y2cw== X-Gm-Message-State: AD7BkJKAHKR4/8jwyQK2dOzN3wLpJVclQd6P/DgRjvqKebVosGqF/FDaF6DjX9uPgIrGOL+H X-Received: by 10.194.24.39 with SMTP id r7mr10417825wjf.86.1458838239996; Thu, 24 Mar 2016 09:50:39 -0700 (PDT) Received: from localhost.localdomain ([90.63.244.31]) by smtp.gmail.com with ESMTPSA id lz5sm8177545wjb.5.2016.03.24.09.50.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 24 Mar 2016 09:50:39 -0700 (PDT) From: Neil Armstrong To: linux-kernel@vger.kernel.org, linux@arm.linux.org.uk, linux-arm-kernel@lists.infradead.org, daniel.lezcano@linaro.org, tglx@linutronix.de, rmk+kernel@arm.linux.org.uk, sudeep.holla@arm.com Subject: [PATCH v3 01/18] clocksource: sp804: Add support for OX810SE 24bit timer width Date: Thu, 24 Mar 2016 17:49:58 +0100 Message-Id: <1458838215-23314-2-git-send-email-narmstrong@baylibre.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1458838215-23314-1-git-send-email-narmstrong@baylibre.com> References: <1458838215-23314-1-git-send-email-narmstrong@baylibre.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160324_095102_054103_36D2A84F X-CRM114-Status: GOOD ( 15.54 ) X-Spam-Score: -1.9 (-) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Neil Armstrong MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP In order to support the Dual-Timer on the PLX Technology OX810SE SoC, implement variable counter width, keeping 32bit as default width. Add new compatible string oxsemi,ox810se-rps-timer in order to select the 24bit counter width. Signed-off-by: Neil Armstrong --- drivers/clocksource/timer-sp804.c | 40 ++++++++++++++++++++++++++------------- include/clocksource/timer-sp804.h | 11 ++++++----- 2 files changed, 33 insertions(+), 18 deletions(-) diff --git a/drivers/clocksource/timer-sp804.c b/drivers/clocksource/timer-sp804.c index 5f45b9a..bdf3e14 100644 --- a/drivers/clocksource/timer-sp804.c +++ b/drivers/clocksource/timer-sp804.c @@ -80,9 +80,11 @@ void __init sp804_timer_disable(void __iomem *base) void __init __sp804_clocksource_and_sched_clock_init(void __iomem *base, const char *name, struct clk *clk, - int use_sched_clock) + int use_sched_clock, + unsigned int width) { long rate; + u32 config = TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC; if (!clk) { clk = clk_get_sys("sp804", name); @@ -98,19 +100,21 @@ void __init __sp804_clocksource_and_sched_clock_init(void __iomem *base, if (rate < 0) return; + if (width == 32) + config |= TIMER_CTRL_32BIT; + /* setup timer 0 as free-running clocksource */ writel(0, base + TIMER_CTRL); writel(0xffffffff, base + TIMER_LOAD); writel(0xffffffff, base + TIMER_VALUE); - writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC, - base + TIMER_CTRL); + writel(config, base + TIMER_CTRL); clocksource_mmio_init(base + TIMER_VALUE, name, - rate, 200, 32, clocksource_mmio_readl_down); + rate, 200, width, clocksource_mmio_readl_down); if (use_sched_clock) { sched_clock_base = base; - sched_clock_register(sp804_read, 32, rate); + sched_clock_register(sp804_read, width, rate); } } @@ -186,7 +190,9 @@ static struct irqaction sp804_timer_irq = { .dev_id = &sp804_clockevent, }; -void __init __sp804_clockevents_init(void __iomem *base, unsigned int irq, struct clk *clk, const char *name) +void __init __sp804_clockevents_init(void __iomem *base, unsigned int irq, + struct clk *clk, const char *name, + unsigned int width) { struct clock_event_device *evt = &sp804_clockevent; long rate; @@ -212,7 +218,7 @@ void __init __sp804_clockevents_init(void __iomem *base, unsigned int irq, struc writel(0, base + TIMER_CTRL); setup_irq(irq, &sp804_timer_irq); - clockevents_config_and_register(evt, rate, 0xf, 0xffffffff); + clockevents_config_and_register(evt, rate, 0xf, GENMASK(width-1, 0)); } static void __init sp804_of_init(struct device_node *np) @@ -223,6 +229,7 @@ static void __init sp804_of_init(struct device_node *np) u32 irq_num = 0; struct clk *clk1, *clk2; const char *name = of_get_property(np, "compatible", NULL); + u32 width = 32; base = of_iomap(np, 0); if (WARN_ON(!base)) @@ -254,14 +261,19 @@ static void __init sp804_of_init(struct device_node *np) if (irq <= 0) goto err; + if (of_device_is_compatible(np, "oxsemi,ox810se-rps-timer")) + width = 24; + of_property_read_u32(np, "arm,sp804-has-irq", &irq_num); if (irq_num == 2) { - __sp804_clockevents_init(base + TIMER_2_BASE, irq, clk2, name); - __sp804_clocksource_and_sched_clock_init(base, name, clk1, 1); + __sp804_clockevents_init(base + TIMER_2_BASE, irq, + clk2, name, width); + __sp804_clocksource_and_sched_clock_init(base, name, + clk1, 1, width); } else { - __sp804_clockevents_init(base, irq, clk1 , name); + __sp804_clockevents_init(base, irq, clk1, name, width); __sp804_clocksource_and_sched_clock_init(base + TIMER_2_BASE, - name, clk2, 1); + name, clk2, 1, width); } initialized = true; @@ -270,6 +282,7 @@ err: iounmap(base); } CLOCKSOURCE_OF_DECLARE(sp804, "arm,sp804", sp804_of_init); +CLOCKSOURCE_OF_DECLARE(ox810se, "oxsemi,ox810se-rps-timer", sp804_of_init); static void __init integrator_cp_of_init(struct device_node *np) { @@ -293,13 +306,14 @@ static void __init integrator_cp_of_init(struct device_node *np) goto err; if (!init_count) - __sp804_clocksource_and_sched_clock_init(base, name, clk, 0); + __sp804_clocksource_and_sched_clock_init(base, name, + clk, 0, 32); else { irq = irq_of_parse_and_map(np, 0); if (irq <= 0) goto err; - __sp804_clockevents_init(base, irq, clk, name); + __sp804_clockevents_init(base, irq, clk, name, 32); } init_count++; diff --git a/include/clocksource/timer-sp804.h b/include/clocksource/timer-sp804.h index 1f8a1ca..893d730 100644 --- a/include/clocksource/timer-sp804.h +++ b/include/clocksource/timer-sp804.h @@ -4,25 +4,26 @@ struct clk; void __sp804_clocksource_and_sched_clock_init(void __iomem *, - const char *, struct clk *, int); + const char *, struct clk *, + int, unsigned int); void __sp804_clockevents_init(void __iomem *, unsigned int, - struct clk *, const char *); + struct clk *, const char *, unsigned int); void sp804_timer_disable(void __iomem *); static inline void sp804_clocksource_init(void __iomem *base, const char *name) { - __sp804_clocksource_and_sched_clock_init(base, name, NULL, 0); + __sp804_clocksource_and_sched_clock_init(base, name, NULL, 0, 32); } static inline void sp804_clocksource_and_sched_clock_init(void __iomem *base, const char *name) { - __sp804_clocksource_and_sched_clock_init(base, name, NULL, 1); + __sp804_clocksource_and_sched_clock_init(base, name, NULL, 1, 32); } static inline void sp804_clockevents_init(void __iomem *base, unsigned int irq, const char *name) { - __sp804_clockevents_init(base, irq, NULL, name); + __sp804_clockevents_init(base, irq, NULL, name, 32); } #endif