From patchwork Thu Mar 24 23:51:31 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Lechner X-Patchwork-Id: 8666751 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 1DF479F326 for ; Thu, 24 Mar 2016 23:57:57 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 1AC9A20125 for ; Thu, 24 Mar 2016 23:57:56 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 16BF220115 for ; Thu, 24 Mar 2016 23:57:55 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ajF6v-0002jn-6v; Thu, 24 Mar 2016 23:56:17 +0000 Received: from [50.115.127.205] (helo=vern.gendns.com) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ajF5d-0000i1-9V for linux-arm-kernel@lists.infradead.org; Thu, 24 Mar 2016 23:54:59 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lechnology.com; s=default; h=References:In-Reply-To:Message-Id:Date:Subject :Cc:To:From; bh=+ym5uX8dZR7phYdM69qJntfhTMAA/QBDW5OaSQR09Mo=; b=qBpCRWE0OmovN 6GC6q2TeK0HtwXGd5vx7omkniZCISg0qf6tN4TPFU0HesfQh8eJlIzwLIFoLALdhZqhtSj2yAo2dG 0NcSH2cOC79tWcoUVK/UpAQn5gsMzHcEeqrkl+ukJMvW3kiQGCa4Qiv8to1UQUqgpyrGBd8fRXz4+ I3haZ6igsdsriwCuqH1FYF3bYtcrNvTg26EZxC7KC50RB7ylxE9w7seZB/6EmUqWvFieL8VOCx4+1 FeJzIZ34GXI4WgpTPY3YU20+i6LPN2CAYSQtrd0vuThtv8S9HYsPcN9m1p4dM7l9aBKqB1au8uxL5 fGPCPATbmOPmlAzj1rP1Q==; Received: from 108-198-5-147.lightspeed.okcbok.sbcglobal.net ([108.198.5.147]:47864 helo=freyr.lechnology.com) by vern.gendns.com with esmtpsa (TLSv1.2:ECDHE-RSA-AES128-SHA256:128) (Exim 4.86_1) (envelope-from ) id 1ajF4J-000XIt-Er; Thu, 24 Mar 2016 19:53:35 -0400 From: David Lechner To: Subject: [PATCH v3 06/16] ARM: davinci: da850: use clk->set_parent for async3 Date: Thu, 24 Mar 2016 18:51:31 -0500 Message-Id: <1458863503-31121-7-git-send-email-david@lechnology.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1458863503-31121-1-git-send-email-david@lechnology.com> References: <1458863503-31121-1-git-send-email-david@lechnology.com> X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - vern.gendns.com X-AntiAbuse: Original Domain - lists.infradead.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - lechnology.com X-Get-Message-Sender-Via: vern.gendns.com: authenticated_id: davidmain+lechnology.com/only user confirmed/virtual account not confirmed X-Authenticated-Sender: vern.gendns.com: davidmain@lechnology.com X-Source: X-Source-Args: X-Source-Dir: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160324_165457_516072_00BF701E X-CRM114-Status: GOOD ( 14.51 ) X-Spam-Score: -0.5 (/) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , "open list:USB SUBSYSTEM" , Russell King , David Lechner , Pawel Moll , Ian Campbell , Greg Kroah-Hartman , Kevin Hilman , Sekhar Nori , open list , Kishon Vijay Abraham I , petr@barix.com, Rob Herring , Alan Stern , "moderated list:ARM PORT" , Kumar Gala , David.Laight@ACULAB.COM, Lee Jones , sergei.shtylyov@cogentembedded.com, Bin Liu MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The da850 family of processors has an async3 clock domain that can be muxed to either pll0_sysclk2 or pll1_sysclk2. Now that the davinci clocks have a set_parent callback, we can use this to control the async3 mux instead of a stand-alone function. This adds a new async3_clk and sets the appropriate child clocks. The default is use to pll1_sysclk2 since it is not affected by processor frequency scaling. Signed-off-by: David Lechner --- v3 changes: * Does not use ioremap in da850_async3_set_parent(). This works now becuase the clock init has been moved. * Fixed copy/paste error in a comment. arch/arm/mach-davinci/da850.c | 82 ++++++++++++++++++------------------------- 1 file changed, 34 insertions(+), 48 deletions(-) diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c index 9f46706..10bfbed 100644 --- a/arch/arm/mach-davinci/da850.c +++ b/arch/arm/mach-davinci/da850.c @@ -34,9 +34,6 @@ #include "clock.h" #include "mux.h" -/* SoC specific clock flags */ -#define DA850_CLK_ASYNC3 BIT(16) - #define DA850_PLL1_BASE 0x01e1a000 #define DA850_TIMER64P2_BASE 0x01f0c000 #define DA850_TIMER64P3_BASE 0x01f0d000 @@ -161,6 +158,33 @@ static struct clk pll1_sysclk3 = { .div_reg = PLLDIV3, }; +static int da850_async3_set_parent(struct clk *clk, struct clk *parent) +{ + u32 val; + + val = readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG)); + + /* Set the Async3 clock domain mux based on the parent clock. */ + if (parent == &pll0_sysclk2) + val &= ~CFGCHIP3_ASYNC3_CLKSRC; + else if (parent == &pll1_sysclk2) + val |= CFGCHIP3_ASYNC3_CLKSRC; + else { + pr_err("Bad parent on async3 clock mux.\n"); + return -EINVAL; + } + + writel(val, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG)); + + return 0; +} + +static struct clk async3_clk = { + .name = "async3", + .parent = &pll1_sysclk2, + .set_parent = da850_async3_set_parent, +}; + static struct clk i2c0_clk = { .name = "i2c0", .parent = &pll0_aux_clk, @@ -234,18 +258,16 @@ static struct clk uart0_clk = { static struct clk uart1_clk = { .name = "uart1", - .parent = &pll0_sysclk2, + .parent = &async3_clk, .lpsc = DA8XX_LPSC1_UART1, .gpsc = 1, - .flags = DA850_CLK_ASYNC3, }; static struct clk uart2_clk = { .name = "uart2", - .parent = &pll0_sysclk2, + .parent = &async3_clk, .lpsc = DA8XX_LPSC1_UART2, .gpsc = 1, - .flags = DA850_CLK_ASYNC3, }; static struct clk aintc_clk = { @@ -300,10 +322,9 @@ static struct clk emac_clk = { static struct clk mcasp_clk = { .name = "mcasp", - .parent = &pll0_sysclk2, + .parent = &async3_clk, .lpsc = DA8XX_LPSC1_McASP0, .gpsc = 1, - .flags = DA850_CLK_ASYNC3, }; static struct clk lcdc_clk = { @@ -355,10 +376,9 @@ static struct clk spi0_clk = { static struct clk spi1_clk = { .name = "spi1", - .parent = &pll0_sysclk2, + .parent = &async3_clk, .lpsc = DA8XX_LPSC1_SPI1, .gpsc = 1, - .flags = DA850_CLK_ASYNC3, }; static struct clk vpif_clk = { @@ -386,10 +406,9 @@ static struct clk dsp_clk = { static struct clk ehrpwm_clk = { .name = "ehrpwm", - .parent = &pll0_sysclk2, + .parent = &async3_clk, .lpsc = DA8XX_LPSC1_PWM, .gpsc = 1, - .flags = DA850_CLK_ASYNC3, }; #define DA8XX_EHRPWM_TBCLKSYNC BIT(12) @@ -421,10 +440,9 @@ static struct clk ehrpwm_tbclk = { static struct clk ecap_clk = { .name = "ecap", - .parent = &pll0_sysclk2, + .parent = &async3_clk, .lpsc = DA8XX_LPSC1_ECAP, .gpsc = 1, - .flags = DA850_CLK_ASYNC3, }; static struct clk_lookup da850_clks[] = { @@ -442,6 +460,7 @@ static struct clk_lookup da850_clks[] = { CLK(NULL, "pll1_aux", &pll1_aux_clk), CLK(NULL, "pll1_sysclk2", &pll1_sysclk2), CLK(NULL, "pll1_sysclk3", &pll1_sysclk3), + CLK(NULL, "async3", &async3_clk), CLK("i2c_davinci.1", NULL, &i2c0_clk), CLK(NULL, "timer0", &timerp64_0_clk), CLK("davinci-wdt", NULL, &timerp64_1_clk), @@ -909,30 +928,6 @@ static struct davinci_timer_info da850_timer_info = { .clocksource_id = T0_TOP, }; -static void da850_set_async3_src(int pllnum) -{ - struct clk *clk, *newparent = pllnum ? &pll1_sysclk2 : &pll0_sysclk2; - struct clk_lookup *c; - unsigned int v; - int ret; - - for (c = da850_clks; c->clk; c++) { - clk = c->clk; - if (clk->flags & DA850_CLK_ASYNC3) { - ret = clk_set_parent(clk, newparent); - WARN(ret, "DA850: unable to re-parent clock %s", - clk->name); - } - } - - v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG)); - if (pllnum) - v |= CFGCHIP3_ASYNC3_CLKSRC; - else - v &= ~CFGCHIP3_ASYNC3_CLKSRC; - __raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG)); -} - #ifdef CONFIG_CPU_FREQ /* * Notes: @@ -1328,15 +1323,6 @@ void __init da850_init(void) if (WARN(!da8xx_syscfg1_base, "Unable to map syscfg1 module")) return; - /* - * Move the clock source of Async3 domain to PLL1 SYSCLK2. - * This helps keeping the peripherals on this domain insulated - * from CPU frequency changes caused by DVFS. The firmware sets - * both PLL0 and PLL1 to the same frequency so, there should not - * be any noticeable change even in non-DVFS use cases. - */ - da850_set_async3_src(1); - /* Unlock writing to PLL0 registers */ v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG)); v &= ~CFGCHIP0_PLL_MASTER_LOCK;