| Message ID | 1459071058-18328-2-git-send-email-thomas.petazzoni@free-electrons.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Sun, Mar 27, 2016 at 11:30:57AM +0200, Thomas Petazzoni wrote: > This commit adds the Device Tree binding documentation that allows to > describe the PCIe controller found in Marvell Armada 7K/8K SoCs. > > Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> > --- > .../devicetree/bindings/pci/pci-armada8k.txt | 41 ++++++++++++++++++++++ > 1 file changed, 41 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pci/pci-armada8k.txt Acked-by: Rob Herring <robh@kernel.org>
On Sunday 27 March 2016 11:30:57 Thomas Petazzoni wrote: > + ranges = <0x81000000 0 0xf9000000 0 0xf9000000 0 0x10000 /* downstream I/O */ > + 0x82000000 0 0xf6000000 0 0xf6000000 0 0xf00000>; /* non-prefetchable memory */ > No 64-bit (prefetchable) MMIO area? Is this a hardware limitation, or did you just forget to add it? Arnd
Arnd, On Mon, 28 Mar 2016 23:18:02 +0200, Arnd Bergmann wrote: > On Sunday 27 March 2016 11:30:57 Thomas Petazzoni wrote: > > + ranges = <0x81000000 0 0xf9000000 0 0xf9000000 0 0x10000 /* downstream I/O */ > > + 0x82000000 0 0xf6000000 0 0xf6000000 0 0xf00000>; /* non-prefetchable memory */ > > > > No 64-bit (prefetchable) MMIO area? Is this a hardware limitation, > or did you just forget to add it? I don't have enough technical documentation at the moment to answer the question. Would it be possible to merge this as-is, and update it later on when we have enough information about 64-bit MMIO area support? It does not affect this new DT binding, since it's purely related to the standard PCI binding. Would this be OK? I'd prefer to have PCI supported with just the 32 bits non-prefetchable memory rather than no PCI supported at all. Thanks a lot! Thomas
diff --git a/Documentation/devicetree/bindings/pci/pci-armada8k.txt b/Documentation/devicetree/bindings/pci/pci-armada8k.txt new file mode 100644 index 0000000..577de5b --- /dev/null +++ b/Documentation/devicetree/bindings/pci/pci-armada8k.txt @@ -0,0 +1,41 @@ +* Marvell Armada 7K/8K PCIe interface + +This PCIe host controller is based on the Synopsis Designware PCIe IP +and thus inherits all the common properties defined in designware-pcie.txt. + +Required properties: +- compatible: "marvell,armada8k-pcie" +- reg: must contain two register regions + - the control register region + - the config space region +- reg-names: + - "ctrl" for the control register region + - "config" for the config space region +- interrupts: Interrupt specifier for the PCIe controler +- clock-names: May contain the following entries: + - "main", for the main clock, shared by several PCIe ports + - "port", for the port clock + +Example: + + pcie@f2600000 { + compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; + reg = <0 0xf2600000 0 0x10000>, <0 0xf6f00000 0 0x80000>; + reg-names = "ctrl", "config"; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + dma-coherent; + + bus-range = <0 0xff>; + ranges = <0x81000000 0 0xf9000000 0 0xf9000000 0 0x10000 /* downstream I/O */ + 0x82000000 0 0xf6000000 0 0xf6000000 0 0xf00000>; /* non-prefetchable memory */ + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + num-lanes = <1>; + clocks = <&cpm_syscon0 1 14>, <&cpm_syscon0 1 13>; + clock-names = "main", "port"; + status = "disabled"; + };
This commit adds the Device Tree binding documentation that allows to describe the PCIe controller found in Marvell Armada 7K/8K SoCs. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> --- .../devicetree/bindings/pci/pci-armada8k.txt | 41 ++++++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/pci-armada8k.txt