Message ID | 1459140510-5317-4-git-send-email-anup.patel@broadcom.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Le 27/03/2016 21:48, Anup Patel a écrit : > Required properties: > - compatible: should be one or more of > "brcm,bcm7425-sata-phy" > "brcm,bcm7445-sata-phy" > + "brcm,iproc-ns2-sata-phy" > "brcm,phy-sata3" > - address-cells: should be 1 > - size-cells: should be 0 > -- reg: register range for the PHY PCB interface > -- reg-names: should be "phy" > +- reg: register ranges for the PHY PCB interface > +- reg-names: should be "phy" and "phy-ctrl" > + The "phy-ctrl" registers are only required for > + "brcm,iproc-ns2-sata-phy". I objected to adding another register during the internal review, which, in the case of the STB chips is dealt with at the AHCI controller level as was requested when Brian got the driver sent, but if that is the only point here, then let's get your patches merged as-is. The rest of the changes look fine so: Acked-by: Florian Fainelli <f.fainelli@gmail.com> -- Florian
diff --git a/Documentation/devicetree/bindings/phy/brcm,brcmstb-sata-phy.txt b/Documentation/devicetree/bindings/phy/brcm-sata-phy.txt similarity index 69% rename from Documentation/devicetree/bindings/phy/brcm,brcmstb-sata-phy.txt rename to Documentation/devicetree/bindings/phy/brcm-sata-phy.txt index d87ab7c..d023120 100644 --- a/Documentation/devicetree/bindings/phy/brcm,brcmstb-sata-phy.txt +++ b/Documentation/devicetree/bindings/phy/brcm-sata-phy.txt @@ -1,14 +1,17 @@ -* Broadcom SATA3 PHY for STB +* Broadcom SATA3 PHY Required properties: - compatible: should be one or more of "brcm,bcm7425-sata-phy" "brcm,bcm7445-sata-phy" + "brcm,iproc-ns2-sata-phy" "brcm,phy-sata3" - address-cells: should be 1 - size-cells: should be 0 -- reg: register range for the PHY PCB interface -- reg-names: should be "phy" +- reg: register ranges for the PHY PCB interface +- reg-names: should be "phy" and "phy-ctrl" + The "phy-ctrl" registers are only required for + "brcm,iproc-ns2-sata-phy". Sub-nodes: Each port's PHY should be represented as a sub-node. @@ -16,12 +19,12 @@ Sub-nodes: Sub-nodes required properties: - reg: the PHY number - phy-cells: generic PHY binding; must be 0 -Optional: -- brcm,enable-ssc: use spread spectrum clocking (SSC) on this port +Sub-nodes optional properties: +- brcm,enable-ssc: use spread spectrum clocking (SSC) on this port + This property is not applicable for "brcm,iproc-ns2-sata-phy". Example: - sata-phy@f0458100 { compatible = "brcm,bcm7445-sata-phy", "brcm,phy-sata3"; reg = <0xf0458100 0x1e00>, <0xf045804c 0x10>;