| Message ID | 1459338921-391-1-git-send-email-jszhang@marvell.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
From: Jisheng Zhang <jszhang@marvell.com> Date: Wed, 30 Mar 2016 19:55:21 +0800 > The mvneta is also used in some Marvell berlin family SoCs which may > have 64bytes cacheline size. Replace the MVNETA_CPU_D_CACHE_LINE_SIZE > usage with L1_CACHE_BYTES. > > And since dma_alloc_coherent() is always cacheline size aligned, so > remove the align checks. > > Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Applied.
Hello, On Thu, 31 Mar 2016 15:15:47 -0400 (EDT), David Miller wrote: > From: Jisheng Zhang <jszhang@marvell.com> > Date: Wed, 30 Mar 2016 19:55:21 +0800 > > > The mvneta is also used in some Marvell berlin family SoCs which may > > have 64bytes cacheline size. Replace the MVNETA_CPU_D_CACHE_LINE_SIZE > > usage with L1_CACHE_BYTES. > > > > And since dma_alloc_coherent() is always cacheline size aligned, so > > remove the align checks. > > > > Signed-off-by: Jisheng Zhang <jszhang@marvell.com> > > Applied. A new version of the patch was sent, which more rightfully uses cache_line_size(), see: "[PATCH v2] net: mvneta: replace MVNETA_CPU_D_CACHE_LINE_SIZE with cache_line_size" Best regards, Thomas
From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Date: Thu, 31 Mar 2016 22:37:35 +0200 > Hello, > > On Thu, 31 Mar 2016 15:15:47 -0400 (EDT), David Miller wrote: >> From: Jisheng Zhang <jszhang@marvell.com> >> Date: Wed, 30 Mar 2016 19:55:21 +0800 >> >> > The mvneta is also used in some Marvell berlin family SoCs which may >> > have 64bytes cacheline size. Replace the MVNETA_CPU_D_CACHE_LINE_SIZE >> > usage with L1_CACHE_BYTES. >> > >> > And since dma_alloc_coherent() is always cacheline size aligned, so >> > remove the align checks. >> > >> > Signed-off-by: Jisheng Zhang <jszhang@marvell.com> >> >> Applied. > > A new version of the patch was sent, which more rightfully uses > cache_line_size(), see: > > "[PATCH v2] net: mvneta: replace MVNETA_CPU_D_CACHE_LINE_SIZE with cache_line_size" Sorry about that. Send me a realtive fixup patch if you like. Thanks.
Hi David, Thomas, On Thu, 31 Mar 2016 16:47:10 -0400 David Miller wrote: > From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> > Date: Thu, 31 Mar 2016 22:37:35 +0200 > > > Hello, > > > > On Thu, 31 Mar 2016 15:15:47 -0400 (EDT), David Miller wrote: > >> From: Jisheng Zhang <jszhang@marvell.com> > >> Date: Wed, 30 Mar 2016 19:55:21 +0800 > >> > >> > The mvneta is also used in some Marvell berlin family SoCs which may > >> > have 64bytes cacheline size. Replace the MVNETA_CPU_D_CACHE_LINE_SIZE > >> > usage with L1_CACHE_BYTES. > >> > > >> > And since dma_alloc_coherent() is always cacheline size aligned, so > >> > remove the align checks. > >> > > >> > Signed-off-by: Jisheng Zhang <jszhang@marvell.com> > >> > >> Applied. > > > > A new version of the patch was sent, which more rightfully uses > > cache_line_size(), see: > > > > "[PATCH v2] net: mvneta: replace MVNETA_CPU_D_CACHE_LINE_SIZE with cache_line_size" > > Sorry about that. > > Send me a realtive fixup patch if you like. > Sorry about inconvenience, I'll send out fixup patch. Thanks, Jisheng
diff --git a/drivers/net/ethernet/marvell/mvneta.c b/drivers/net/ethernet/marvell/mvneta.c index 577f7ca..5880871 100644 --- a/drivers/net/ethernet/marvell/mvneta.c +++ b/drivers/net/ethernet/marvell/mvneta.c @@ -260,7 +260,6 @@ #define MVNETA_VLAN_TAG_LEN 4 -#define MVNETA_CPU_D_CACHE_LINE_SIZE 32 #define MVNETA_TX_CSUM_DEF_SIZE 1600 #define MVNETA_TX_CSUM_MAX_SIZE 9800 #define MVNETA_ACC_MODE_EXT1 1 @@ -300,7 +299,7 @@ #define MVNETA_RX_PKT_SIZE(mtu) \ ALIGN((mtu) + MVNETA_MH_SIZE + MVNETA_VLAN_TAG_LEN + \ ETH_HLEN + ETH_FCS_LEN, \ - MVNETA_CPU_D_CACHE_LINE_SIZE) + L1_CACHE_BYTES) #define IS_TSO_HEADER(txq, addr) \ ((addr >= txq->tso_hdrs_phys) && \ @@ -2764,9 +2763,6 @@ static int mvneta_rxq_init(struct mvneta_port *pp, if (rxq->descs == NULL) return -ENOMEM; - BUG_ON(rxq->descs != - PTR_ALIGN(rxq->descs, MVNETA_CPU_D_CACHE_LINE_SIZE)); - rxq->last_desc = rxq->size - 1; /* Set Rx descriptors queue starting address */ @@ -2837,10 +2833,6 @@ static int mvneta_txq_init(struct mvneta_port *pp, if (txq->descs == NULL) return -ENOMEM; - /* Make sure descriptor address is cache line size aligned */ - BUG_ON(txq->descs != - PTR_ALIGN(txq->descs, MVNETA_CPU_D_CACHE_LINE_SIZE)); - txq->last_desc = txq->size - 1; /* Set maximum bandwidth for enabled TXQs */
The mvneta is also used in some Marvell berlin family SoCs which may have 64bytes cacheline size. Replace the MVNETA_CPU_D_CACHE_LINE_SIZE usage with L1_CACHE_BYTES. And since dma_alloc_coherent() is always cacheline size aligned, so remove the align checks. Signed-off-by: Jisheng Zhang <jszhang@marvell.com> --- drivers/net/ethernet/marvell/mvneta.c | 10 +--------- 1 file changed, 1 insertion(+), 9 deletions(-)