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Thu, 31 Mar 2016 11:48:09 +0900 (KST) From: Chanwoo Choi To: k.kozlowski@samsung.com, kgene@kernel.org, s.nawrocki@samsung.com, tomasz.figa@gmail.com Subject: [PATCH v4 1/9] ARM: dts: Add initial pin configuration for exynos3250-rinato Date: Thu, 31 Mar 2016 11:47:57 +0900 Message-id: <1459392485-11327-2-git-send-email-cw00.choi@samsung.com> X-Mailer: git-send-email 1.8.0 In-reply-to: <1459392485-11327-1-git-send-email-cw00.choi@samsung.com> References: <1459392485-11327-1-git-send-email-cw00.choi@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmpgkeLIzCtJLcpLzFFi42JZI2JSoPuy/0+Ywb0lZhbbjzxjtbj+5Tmr xfwj51gtJt2fwGJx41cbq8XrF4YWvQuusln0P37NbLHp8TVWi8u75rBZzDi/j8li0dYv7BaH 37SzWsyY/JLNYtWuP4wO/B47Z91l99i0qpPNY/OSeo++LasYPT5vkgtgjeKySUnNySxLLdK3 S+DKaNu/mrXgtVLF9ld/2BoY30h3MXJySAiYSFybNJcVwhaTuHBvPVsXIxeHkMAKRomO+W/Y YIrm7/0GViQkMItR4vUXRgj7C6NE5y1PEJtNQEti/4sbYPUiAnESEy9C2MwCB5gkNnbmgtjC AuESW6/tAOtlEVCVaO1tA5vJK+Aq8fb5FhaIXXISH/Y8YgexOQXcJO6tuMwOsctVYs3MOcwg x0kInGKXuNX4gw1ikIDEt8mHgJo5gBKyEpsOMEPMkZQ4uOIGywRG4QWMDKsYRVMLkguKk9KL jPSKE3OLS/PS9ZLzczcxAiPm9L9nfTsYbx6wPsQowMGoxMOrkfYnTIg1say4MvcQoynQhonM UqLJ+cC4zCuJNzQ2M7IwNTE1NjK3NFMS502Q+hksJJCeWJKanZpakFoUX1Sak1p8iJGJg1Oq gTF467vt4qnhc1xUjB+KLVqQ/UQ0fHXzAs2/+RduJ0zgO80Q+KBO5ouFtHfXlskrpRME921I f32Md/tEfQOVkzLSm6bU/Lka/+234u7zihUdtff21Wd84t99VvZlmGOgQb1qQe3axz3v2rZo 35S34Ey8XOoyc9pbcc//i98lRNtU3jNtXdU9102JpTgj0VCLuag4EQDRVN3ikwIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrLIsWRmVeSWpSXmKPExsVy+t9jQd2X/X/CDA4+07fYfuQZq8X1L89Z LeYfOcdqMen+BBaLG7/aWC1evzC06F1wlc2i//FrZotNj6+xWlzeNYfNYsb5fUwWi7Z+Ybc4 /Kad1WLG5JdsFqt2/WF04PfYOesuu8emVZ1sHpuX1Hv0bVnF6PF5k1wAa1QDo01GamJKapFC al5yfkpmXrqtkndwvHO8qZmBoa6hpYW5kkJeYm6qrZKLT4CuW2YO0LVKCmWJOaVAoYDE4mIl fTtME0JD3HQtYBojdH1DguB6jAzQQMIaxoy2/atZC14rVWx/9YetgfGNdBcjJ4eEgInE/L3f WCFsMYkL99azgdhCArMYJV5/YYSwvzBKdN7yBLHZBLQk9r+4AVYjIhAnMfEihM0scIBJYmNn LogtLBAusfXaDrBeFgFVidbeNrD5vAKuEm+fb2GB2CUn8WHPI3YQm1PATeLeisvsELtcJdbM nMM8gZF3ASPDKkaJ1ILkguKk9FyjvNRyveLE3OLSvHS95PzcTYzgqHwmvYPx8C73Q4wCHIxK PLwXkv+ECbEmlhVX5h5ilOBgVhLhDe0DCvGmJFZWpRblxxeV5qQWH2I0BTpsIrOUaHI+MGHk lcQbGpuYGVkamRtaGBmbK4nzPv6/LkxIID2xJDU7NbUgtQimj4mDU6qBce9dT59pdWfuS62v +WYzV86gWGd63S633Fe5jdfZ7qds6j/zujhr+eWn6uFv9TUl/cSOHRBNicvecYSP9/3DBU// zPS251hQYX43mJmhgEFM3OOfi+mtzwe+bz5zMY9bdi4zY3EM+5QF3YoJM66yFf/a+982quvW EUaeTx6rdj1XsLy7R6aAW4mlOCPRUIu5qDgRADPlq3XgAgAA DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160330_194839_019627_9EE880EF X-CRM114-Status: GOOD ( 12.42 ) X-Spam-Score: -7.9 (-------) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: inki.dae@samsung.com, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, pankaj.dubey@samsung.com, sw0312.kim@samsung.com, linux-kernel@vger.kernel.org, andi.shyti@samsung.com, jh80.chung@samsung.com, cw00.choi@samsung.com, Kukjin Kim , linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds initial pin configuration using pinctrl subsystem to reduce leakage power-consumption of gpio pins in normal state. All pins included in this patch are NC (not connected) pin. Cc: Kukjin Kim Cc: Krzysztof Kozlowski Signed-off-by: Chanwoo Choi Reviewed-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos3250-pinctrl.dtsi | 38 +++++++++++++++++ arch/arm/boot/dts/exynos3250-rinato.dts | 71 ++++++++++++++++++++++++++++++- 2 files changed, 107 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi index 5ab81c39e2c9..ecf79386e891 100644 --- a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi @@ -16,11 +16,49 @@ #define PIN_PULL_DOWN 1 #define PIN_PULL_UP 3 +#define PIN_DRV_LV1 0 +#define PIN_DRV_LV2 2 +#define PIN_DRV_LV3 1 +#define PIN_DRV_LV4 3 + #define PIN_PDN_OUT0 0 #define PIN_PDN_OUT1 1 #define PIN_PDN_INPUT 2 #define PIN_PDN_PREV 3 +#define PIN_IN(_pin, _pull, _drv) \ + _pin { \ + samsung,pins = #_pin; \ + samsung,pin-function = <0>; \ + samsung,pin-pud = ; \ + samsung,pin-drv = ; \ + } + +#define PIN_OUT(_pin, _drv) \ + _pin { \ + samsung,pins = #_pin; \ + samsung,pin-function = <1>; \ + samsung,pin-pud = <0>; \ + samsung,pin-drv = ; \ + } + +#define PIN_OUT_SET(_pin, _val, _drv) \ + _pin { \ + samsung,pins = #_pin; \ + samsung,pin-function = <1>; \ + samsung,pin-pud = <0>; \ + samsung,pin-drv = ; \ + samsung,pin-val = <_val>; \ + } + +#define PIN_CFG(_pin, _sel, _pull, _drv) \ + _pin { \ + samsung,pins = #_pin; \ + samsung,pin-function = <_sel>; \ + samsung,pin-pud = ; \ + samsung,pin-drv = ; \ + } + #define PIN_SLP(_pin, _mode, _pull) \ _pin { \ samsung,pins = #_pin; \ diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts b/arch/arm/boot/dts/exynos3250-rinato.dts index 1f102f3a1ab1..31eb09bae0a2 100644 --- a/arch/arm/boot/dts/exynos3250-rinato.dts +++ b/arch/arm/boot/dts/exynos3250-rinato.dts @@ -681,7 +681,21 @@ &pinctrl_0 { pinctrl-names = "default"; - pinctrl-0 = <&sleep0>; + pinctrl-0 = <&initial0 &sleep0>; + + initial0: initial-state { + PIN_IN(gpa1-4, DOWN, LV1); + PIN_IN(gpa1-5, DOWN, LV1); + + PIN_IN(gpc0-0, DOWN, LV1); + PIN_IN(gpc0-1, DOWN, LV1); + PIN_IN(gpc0-2, DOWN, LV1); + PIN_IN(gpc0-3, DOWN, LV1); + PIN_IN(gpc0-4, DOWN, LV1); + + PIN_IN(gpd0-0, DOWN, LV1); + PIN_IN(gpd0-1, DOWN, LV1); + }; sleep0: sleep-state { PIN_SLP(gpa0-0, INPUT, DOWN); @@ -735,7 +749,60 @@ &pinctrl_1 { pinctrl-names = "default"; - pinctrl-0 = <&sleep1>; + pinctrl-0 = <&initial1 &sleep1>; + + initial1: initial-state { + PIN_IN(gpe0-6, DOWN, LV1); + PIN_IN(gpe0-7, DOWN, LV1); + + PIN_IN(gpe1-0, DOWN, LV1); + PIN_IN(gpe1-3, DOWN, LV1); + PIN_IN(gpe1-4, DOWN, LV1); + PIN_IN(gpe1-5, DOWN, LV1); + PIN_IN(gpe1-6, DOWN, LV1); + + PIN_IN(gpk2-0, DOWN, LV1); + PIN_IN(gpk2-1, DOWN, LV1); + PIN_IN(gpk2-2, DOWN, LV1); + PIN_IN(gpk2-3, DOWN, LV1); + PIN_IN(gpk2-4, DOWN, LV1); + PIN_IN(gpk2-5, DOWN, LV1); + PIN_IN(gpk2-6, DOWN, LV1); + + PIN_IN(gpm0-0, DOWN, LV1); + PIN_IN(gpm0-1, DOWN, LV1); + PIN_IN(gpm0-2, DOWN, LV1); + PIN_IN(gpm0-3, DOWN, LV1); + PIN_IN(gpm0-4, DOWN, LV1); + PIN_IN(gpm0-5, DOWN, LV1); + PIN_IN(gpm0-6, DOWN, LV1); + PIN_IN(gpm0-7, DOWN, LV1); + + PIN_IN(gpm1-0, DOWN, LV1); + PIN_IN(gpm1-1, DOWN, LV1); + PIN_IN(gpm1-2, DOWN, LV1); + PIN_IN(gpm1-3, DOWN, LV1); + PIN_IN(gpm1-4, DOWN, LV1); + PIN_IN(gpm1-5, DOWN, LV1); + PIN_IN(gpm1-6, DOWN, LV1); + + PIN_IN(gpm2-0, DOWN, LV1); + PIN_IN(gpm2-1, DOWN, LV1); + + PIN_IN(gpm3-0, DOWN, LV1); + PIN_IN(gpm3-1, DOWN, LV1); + PIN_IN(gpm3-2, DOWN, LV1); + PIN_IN(gpm3-3, DOWN, LV1); + PIN_IN(gpm3-4, DOWN, LV1); + + PIN_IN(gpm4-1, DOWN, LV1); + PIN_IN(gpm4-2, DOWN, LV1); + PIN_IN(gpm4-3, DOWN, LV1); + PIN_IN(gpm4-4, DOWN, LV1); + PIN_IN(gpm4-5, DOWN, LV1); + PIN_IN(gpm4-6, DOWN, LV1); + PIN_IN(gpm4-7, DOWN, LV1); + }; sleep1: sleep-state { PIN_SLP(gpe0-0, PREV, NONE);