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Thu, 31 Mar 2016 18:06:08 +0900 (KST) From: Chanwoo Choi To: myungjoo.ham@samsung.com, kyungmin.park@samsung.com, k.kozlowski@samsung.com, kgene@kernel.org Subject: [PATCH v7 16/20] ARM: dts: Add bus nodes using VDD_MIF for Exynos4210 Date: Thu, 31 Mar 2016 18:06:01 +0900 Message-id: <1459415165-32613-17-git-send-email-cw00.choi@samsung.com> X-Mailer: git-send-email 1.8.0 In-reply-to: <1459415165-32613-1-git-send-email-cw00.choi@samsung.com> References: <1459415165-32613-1-git-send-email-cw00.choi@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrLIsWRmVeSWpSXmKPExsWyRsSkULfxxZ8wgyf3JS2uf3nOajH/yDlW i/43C1ktzr1ayWgx6f4EFovXLwwt+h+/ZrY42/SG3WLT42usFpd3zWGz+Nx7hNFixvl9TBbr Nt5it7h9mdfi5ZEfjBZLr19ksrjduILNYsL0tSwWZ05fYrVo3XuE3aJt9QdWB1GPNfPWMHq0 NPeweVzu62XyuHWn3mPnrLvsHiuXf2Hz2LSqk81j85J6j3/H2D22XG1n8ejbsorR4/MmuQCe KC6blNSczLLUIn27BK6MrhXCBbtUKr5fUmpgfC7TxcjJISFgIjF5y21WCFtM4sK99WxdjFwc QgIrGCW+f1vEBFP05N4mdojELEaJx/MOMoMkhAS+MEpcnWUHYrMJaEnsf3GDDcQWEUiRePzw JNgkZoEjzBJTN94AmyQs4Ccxdc4LoEkcHCwCqhJLD3KDhHkF3CRmPWqAWiYn8WHPI3YQmxMo fn/+fahdrhKHlrxiApkpIbCWQ2Lv4t1gZ7MICEh8m3yIBWSmhICsxKYDzBBzJCUOrrjBMoFR eAEjwypG0dSC5ILipPQiI73ixNzi0rx0veT83E2MwFg9/e9Z3w7GmwesDzEKcDAq8fBqpP0J E2JNLCuuzD3EaAq0YSKzlGhyPjAh5JXEGxqbGVmYmpgaG5lbmimJ8yZI/QwWEkhPLEnNTk0t SC2KLyrNSS0+xMjEwSnVwNi3VF109taOjg/8zHuNJq9dXKO2QbCV51drwOxp6jYvv7ge61HZ zO99UrNQytfl8jmX3b8l1zN/5Ul4+Ur0+YfeoImrT3xs3uJ6NmH+YUVutmenkvRvFF97aHo5 /tKqg2Zm29a+l8orvXKn9VlRzO+jrL7tV/dOlSu9ZbFj09o2jaMzWzvW/p2ixFKckWioxVxU nAgAWhfUn9ACAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupileLIzCtJLcpLzFFi42I5/e+xoG7jiz9hBlPahCyuf3nOajH/yDlW i/43C1ktzr1ayWgx6f4EFovXLwwt+h+/ZrY42/SG3WLT42usFpd3zWGz+Nx7hNFixvl9TBbr Nt5it7h9mdfi5ZEfjBZLr19ksrjduILNYsL0tSwWZ05fYrVo3XuE3aJt9QdWB1GPNfPWMHq0 NPeweVzu62XyuHWn3mPnrLvsHiuXf2Hz2LSqk81j85J6j3/H2D22XG1n8ejbsorR4/MmuQCe qAZGm4zUxJTUIoXUvOT8lMy8dFsl7+B453hTMwNDXUNLC3MlhbzE3FRbJRefAF23zBygX5UU yhJzSoFCAYnFxUr6dpgmhIa46VrANEbo+oYEwfUYGaCBhDWMGV0rhAt2qVR8v6TUwPhcpouR k0NCwETiyb1N7BC2mMSFe+vZuhi5OIQEZjFKPJ53kBkkISTwhVHi6iw7EJtNQEti/4sbbCC2 iECKxOOHJ8EamAWOMEtM3XiDCSQhLOAnMXXOC6CpHBwsAqoSSw9yg4R5BdwkZj1qYIJYJifx Yc8jsMWcQPH78+9D7XKVOLTkFdMERt4FjAyrGCVSC5ILipPScw3zUsv1ihNzi0vz0vWS83M3 MYLTwTOpHYwHd7kfYhTgYFTi4b2Q/CdMiDWxrLgy9xCjBAezkgjv3ytAId6UxMqq1KL8+KLS nNTiQ4ymQHdNZJYSTc4Hpqq8knhDYxMzI0sjc0MLI2NzJXHex//XhQkJpCeWpGanphakFsH0 MXFwSjUwxmScXTbjnNeErSzfGfaxv0nQls4Pqr2gFaKx2++WasArp911f46k8kaErP0h8CtF K8Nya28z66e8Izu3Hco1/Xv21ucfdTaPGTY9r4tJNlYSvH1yRZmI4KusmANm+3titZRdNv1l +/j883cWy0ZZ7Si5pwffiWeb+21utHKM4ZC8Nv2KhO99JZbijERDLeai4kQAqIKrWR0DAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160331_020655_121183_C57AECC7 X-CRM114-Status: GOOD ( 10.61 ) X-Spam-Score: -7.9 (-------) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, inki.dae@samsung.com, linux-samsung-soc@vger.kernel.org, linux@arm.linux.org.uk, cw00.choi@samsung.com, pawel.moll@arm.com, ijc+devicetree@hellion.org.uk, linux.amoon@gmail.com, linux-pm@vger.kernel.org, rjw@rjwysocki.net, linux-kernel@vger.kernel.org, m.reichl@fivetechno.de, tjakobi@math.uni-bielefeld.de, devicetree@vger.kernel.org, robh+dt@kernel.org, galak@codeaurora.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds the bus nodes for Exynos4210 SoC. Exynos4210 SoC has one power line for all buses to translate data between DRAM and sub-blocks. Following list specifies the detailed relation between DRAM and sub-blocks: - DMC/ACP clock for DMC (Dynamic Memory Controller) - ACLK200 clock for LCD0 - ACLK100 clock for PERIL/PERIR/MFC(PCLK) - ACLK160 clock for CAM/TV/LCD0/LCD1 - ACLK133 clock for FSYS/GPS - GDL/GDR clock for LEFTBUS/RIGHTBUS - SCLK_MFC clock for MFC Signed-off-by: Chanwoo Choi Reviewed-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos4210.dtsi | 159 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 159 insertions(+) diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi index c1cb8df6da07..2d9b02967105 100644 --- a/arch/arm/boot/dts/exynos4210.dtsi +++ b/arch/arm/boot/dts/exynos4210.dtsi @@ -257,6 +257,165 @@ power-domains = <&pd_lcd1>; #iommu-cells = <0>; }; + + bus_dmc: bus_dmc { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DIV_DMC>; + clock-names = "bus"; + operating-points-v2 = <&bus_dmc_opp_table>; + status = "disabled"; + }; + + bus_acp: bus_acp { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DIV_ACP>; + clock-names = "bus"; + operating-points-v2 = <&bus_acp_opp_table>; + status = "disabled"; + }; + + bus_peri: bus_peri { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_ACLK100>; + clock-names = "bus"; + operating-points-v2 = <&bus_peri_opp_table>; + status = "disabled"; + }; + + bus_fsys: bus_fsys { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_ACLK133>; + clock-names = "bus"; + operating-points-v2 = <&bus_fsys_opp_table>; + status = "disabled"; + }; + + bus_display: bus_display { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_ACLK160>; + clock-names = "bus"; + operating-points-v2 = <&bus_display_opp_table>; + status = "disabled"; + }; + + bus_lcd0: bus_lcd0 { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_ACLK200>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_leftbus: bus_leftbus { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DIV_GDL>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_rightbus: bus_rightbus { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DIV_GDR>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_mfc: bus_mfc { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_SCLK_MFC>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_dmc_opp_table: opp_table1 { + compatible = "operating-points-v2"; + opp-shared; + + opp@134000000 { + opp-hz = /bits/ 64 <134000000>; + opp-microvolt = <1025000>; + }; + opp@267000000 { + opp-hz = /bits/ 64 <267000000>; + opp-microvolt = <1050000>; + }; + opp@400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <1150000>; + }; + }; + + bus_acp_opp_table: opp_table2 { + compatible = "operating-points-v2"; + opp-shared; + + opp@134000000 { + opp-hz = /bits/ 64 <134000000>; + }; + opp@160000000 { + opp-hz = /bits/ 64 <160000000>; + }; + opp@200000000 { + opp-hz = /bits/ 64 <200000000>; + }; + }; + + bus_peri_opp_table: opp_table3 { + compatible = "operating-points-v2"; + opp-shared; + + opp@5000000 { + opp-hz = /bits/ 64 <5000000>; + }; + opp@100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + }; + + bus_fsys_opp_table: opp_table4 { + compatible = "operating-points-v2"; + opp-shared; + + opp@10000000 { + opp-hz = /bits/ 64 <10000000>; + }; + opp@134000000 { + opp-hz = /bits/ 64 <134000000>; + }; + }; + + bus_display_opp_table: opp_table5 { + compatible = "operating-points-v2"; + opp-shared; + + opp@100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + opp@134000000 { + opp-hz = /bits/ 64 <134000000>; + }; + opp@160000000 { + opp-hz = /bits/ 64 <160000000>; + }; + }; + + bus_leftbus_opp_table: opp_table6 { + compatible = "operating-points-v2"; + opp-shared; + + opp@100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + opp@160000000 { + opp-hz = /bits/ 64 <160000000>; + }; + opp@200000000 { + opp-hz = /bits/ 64 <200000000>; + }; + }; }; &gic {