diff mbox

[PATCHv2,7/7] ARM: dts: Add Altera Arria10 OCRAM EDAC devicetree entry

Message ID 1459450087-24792-8-git-send-email-tthayer@opensource.altera.com (mailing list archive)
State New, archived
Headers show

Commit Message

tthayer@opensource.altera.com March 31, 2016, 6:48 p.m. UTC 
From: Thor Thayer <tthayer@opensource.altera.com>

Add the device tree entries needed to support the Altera On-Chip
RAM EDAC on the Arria10 chip.

Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
---
v2: No change
---
 arch/arm/boot/dts/socfpga_arria10.dtsi |    5 +++++
 1 file changed, 5 insertions(+)

Comments

dinguyen@opensource.altera.com April 5, 2016, 6:44 p.m. UTC | #1 
On Thu, 31 Mar 2016, tthayer@opensource.altera.com wrote:

> From: Thor Thayer <tthayer@opensource.altera.com>
> 
> Add the device tree entries needed to support the Altera On-Chip
> RAM EDAC on the Arria10 chip.
> 
> Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
> ---
> v2: No change
> ---
>  arch/arm/boot/dts/socfpga_arria10.dtsi |    5 +++++
>  1 file changed, 5 insertions(+)

I've applied this patch and will take through the arm-soc tree.

Thanks,
Dinh
diff mbox

Patch

diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi
index 519e9e4..27cc497 100644
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -612,6 +612,11 @@ 
 				compatible = "altr,socfpga-a10-l2-ecc";
 				reg = <0xffd06010 0x4>;
 			};
+
+			ocram-ecc@ff8c3000 {
+				compatible = "altr,socfpga-a10-ocram-ecc";
+				reg = <0xff8c3000 0x400>;
+			};
 		};
 
 		rst: rstmgr@ffd05000 {