From patchwork Fri Apr 1 14:22:38 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 8725181 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 5B2C1C0553 for ; Fri, 1 Apr 2016 14:25:28 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 35996203C3 for ; Fri, 1 Apr 2016 14:25:27 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1D58C203B6 for ; Fri, 1 Apr 2016 14:25:26 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1alzz1-0004tT-AD; Fri, 01 Apr 2016 14:23:31 +0000 Received: from mail-wm0-x22e.google.com ([2a00:1450:400c:c09::22e]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1alzyn-0004XM-Qf for linux-arm-kernel@lists.infradead.org; Fri, 01 Apr 2016 14:23:21 +0000 Received: by mail-wm0-x22e.google.com with SMTP id p65so28182493wmp.1 for ; Fri, 01 Apr 2016 07:22:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=/dnqZzbbVhRHV/PuuHn2RVruHzxiyngGvP1KeVrX68M=; b=XvX7NlcfyPXDYWTfISm9rJn2Vk+dy41Eyp/ZQ5yxrjp+gb1aF6tbPOglnCFmFY4AgN XHvoszXeNxSGVfMg5xtcMN9+BMorWRJObZopCpmU4XwxR5Fk4RIQE3Bc2GZPhjj7BXEr z9gaF91kwvKgquwxUHPIBEcVQmorDivFG0Z+VXgstL8qd2K7z6WGuCAL9ExVLnpgnWJL UPIFvIw49d7t1Mdk0CgENTBdm8qcRyZT7CTkOHLZkiMoLcoYx2nOWxZisUkYhqRcVUSL x6Q8SuxbqEjRpUxq1igkoxE00ZXBSEbUlJxGK/mtIr0N7NMIOIm+t4EymEFa1vNUc98g ZR5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=/dnqZzbbVhRHV/PuuHn2RVruHzxiyngGvP1KeVrX68M=; b=jh554EUuY01psq4P7bF89ZbsL0j7EtEoXLeRmNnM6jp/EnilK62RXBCHWhkxKFR+JQ i1q7i/XM65Cb8ZMbzd7c6uP2XjEbLI7egZyqsrfJBnmk9/a6LW1lWOEfo1kxOcLWmkYR /2fGcXb1+KIy5vmQByZZCre9VEjQ6hRRNBdtimVM1DP+2oCMEFieseaoj5WifksMJkCg z0HAtegzjqoezYB5/rJnff/NlPL//g2ug7stjQwbJh18Cx52hScjfZxo1vvj8a7xcQlD LPlgF2tLWh5uumb/PBNAawijtQql2Z6YYNKF+WC8B4B8+lIINJu3KwrC2vMW/Gs42tr8 A4Aw== X-Gm-Message-State: AD7BkJKGnRdFlcwZdjJyKEuifCI8gZKvcBkMIlVoc3zGrinenlz8EeM2CQ0EJguOvt64YZ+J X-Received: by 10.28.57.214 with SMTP id g205mr2282622wma.24.1459520576187; Fri, 01 Apr 2016 07:22:56 -0700 (PDT) Received: from localhost.localdomain ([90.63.244.31]) by smtp.gmail.com with ESMTPSA id s66sm30221600wmb.6.2016.04.01.07.22.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 01 Apr 2016 07:22:55 -0700 (PDT) From: Neil Armstrong To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, daniel.lezcano@linaro.org, tglx@linutronix.de, rmk+kernel@arm.linux.org.uk, sudeep.holla@arm.com Subject: [PATCH 1/2] clocksource: sp804: Add support for OX810SE 24bit timer width Date: Fri, 1 Apr 2016 16:22:38 +0200 Message-Id: <1459520559-13110-2-git-send-email-narmstrong@baylibre.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1459520559-13110-1-git-send-email-narmstrong@baylibre.com> References: <1459520559-13110-1-git-send-email-narmstrong@baylibre.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160401_072318_275229_EE7F5595 X-CRM114-Status: GOOD ( 17.99 ) X-Spam-Score: -1.9 (-) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Neil Armstrong MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP In order to support the Dual-Timer on the Oxford Semiconductor OX810SE SoC, implement variable counter width, keeping 32bit as default width. Add new compatible string oxsemi,ox810se-rps-timer in order to select the 24bit counter width. Signed-off-by: Neil Armstrong --- drivers/clocksource/timer-sp804.c | 107 ++++++++++++++++++++++++-------------- include/clocksource/timer-sp804.h | 42 ++++++++++++--- 2 files changed, 102 insertions(+), 47 deletions(-) diff --git a/drivers/clocksource/timer-sp804.c b/drivers/clocksource/timer-sp804.c index 5f45b9a..e99269a 100644 --- a/drivers/clocksource/timer-sp804.c +++ b/drivers/clocksource/timer-sp804.c @@ -77,15 +77,15 @@ void __init sp804_timer_disable(void __iomem *base) writel(0, base + TIMER_CTRL); } -void __init __sp804_clocksource_and_sched_clock_init(void __iomem *base, - const char *name, - struct clk *clk, - int use_sched_clock) +void __init __sp804_clocksource_and_sched_clock_init(struct timer_sp804 *sp804, + bool use_sched_clock) { long rate; + u32 config = TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC; + struct clk *clk = sp804->clocksource_clk; if (!clk) { - clk = clk_get_sys("sp804", name); + clk = clk_get_sys("sp804", sp804->name); if (IS_ERR(clk)) { pr_err("sp804: clock not found: %d\n", (int)PTR_ERR(clk)); @@ -98,19 +98,22 @@ void __init __sp804_clocksource_and_sched_clock_init(void __iomem *base, if (rate < 0) return; + if (sp804->width == 32) + config |= TIMER_CTRL_32BIT; + /* setup timer 0 as free-running clocksource */ - writel(0, base + TIMER_CTRL); - writel(0xffffffff, base + TIMER_LOAD); - writel(0xffffffff, base + TIMER_VALUE); - writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC, - base + TIMER_CTRL); + writel(0, sp804->clocksource_base + TIMER_CTRL); + writel(0xffffffff, sp804->clocksource_base + TIMER_LOAD); + writel(0xffffffff, sp804->clocksource_base + TIMER_VALUE); + writel(config, sp804->clocksource_base + TIMER_CTRL); - clocksource_mmio_init(base + TIMER_VALUE, name, - rate, 200, 32, clocksource_mmio_readl_down); + clocksource_mmio_init(sp804->clocksource_base + TIMER_VALUE, + sp804->name, rate, 200, sp804->width, + clocksource_mmio_readl_down); if (use_sched_clock) { - sched_clock_base = base; - sched_clock_register(sp804_read, 32, rate); + sched_clock_base = sp804->clocksource_base; + sched_clock_register(sp804_read, sp804->width, rate); } } @@ -186,15 +189,16 @@ static struct irqaction sp804_timer_irq = { .dev_id = &sp804_clockevent, }; -void __init __sp804_clockevents_init(void __iomem *base, unsigned int irq, struct clk *clk, const char *name) +void __init __sp804_clockevents_init(struct timer_sp804 *sp804) { struct clock_event_device *evt = &sp804_clockevent; long rate; + struct clk *clk = sp804->clockevent_clk; if (!clk) - clk = clk_get_sys("sp804", name); + clk = clk_get_sys("sp804", sp804->name); if (IS_ERR(clk)) { - pr_err("sp804: %s clock not found: %d\n", name, + pr_err("sp804: %s clock not found: %d\n", sp804->name, (int)PTR_ERR(clk)); return; } @@ -203,26 +207,27 @@ void __init __sp804_clockevents_init(void __iomem *base, unsigned int irq, struc if (rate < 0) return; - clkevt_base = base; + clkevt_base = sp804->clockevent_base; clkevt_reload = DIV_ROUND_CLOSEST(rate, HZ); - evt->name = name; - evt->irq = irq; + evt->name = sp804->name; + evt->irq = sp804->irq; evt->cpumask = cpu_possible_mask; - writel(0, base + TIMER_CTRL); + writel(0, sp804->clockevent_base + TIMER_CTRL); - setup_irq(irq, &sp804_timer_irq); - clockevents_config_and_register(evt, rate, 0xf, 0xffffffff); + setup_irq(sp804->irq, &sp804_timer_irq); + clockevents_config_and_register(evt, rate, 0xf, + GENMASK(sp804->width-1, 0)); } static void __init sp804_of_init(struct device_node *np) { static bool initialized = false; + struct timer_sp804 sp804; void __iomem *base; - int irq; u32 irq_num = 0; struct clk *clk1, *clk2; - const char *name = of_get_property(np, "compatible", NULL); + u32 width = 32; base = of_iomap(np, 0); if (WARN_ON(!base)) @@ -250,19 +255,33 @@ static void __init sp804_of_init(struct device_node *np) } else clk2 = clk1; - irq = irq_of_parse_and_map(np, 0); - if (irq <= 0) + sp804.irq = irq_of_parse_and_map(np, 0); + if (sp804.irq <= 0) goto err; + /* OX810SE Uses a special 24bit width */ + if (of_device_is_compatible(np, "oxsemi,ox810se-rps-timer")) + width = 24; + of_property_read_u32(np, "arm,sp804-has-irq", &irq_num); if (irq_num == 2) { - __sp804_clockevents_init(base + TIMER_2_BASE, irq, clk2, name); - __sp804_clocksource_and_sched_clock_init(base, name, clk1, 1); + sp804.clockevent_base = base + TIMER_2_BASE; + sp804.clocksource_base = base; + sp804.clockevent_clk = clk2; + sp804.clocksource_clk = clk1; } else { - __sp804_clockevents_init(base, irq, clk1 , name); - __sp804_clocksource_and_sched_clock_init(base + TIMER_2_BASE, - name, clk2, 1); + sp804.clockevent_base = base; + sp804.clocksource_base = base + TIMER_2_BASE; + sp804.clockevent_clk = clk1; + sp804.clocksource_clk = clk2; } + + sp804.name = of_get_property(np, "compatible", NULL); + sp804.width = width; + + __sp804_clockevents_init(&sp804); + __sp804_clocksource_and_sched_clock_init(&sp804, true); + initialized = true; return; @@ -270,13 +289,13 @@ err: iounmap(base); } CLOCKSOURCE_OF_DECLARE(sp804, "arm,sp804", sp804_of_init); +CLOCKSOURCE_OF_DECLARE(ox810se, "oxsemi,ox810se-rps-timer", sp804_of_init); static void __init integrator_cp_of_init(struct device_node *np) { static int init_count = 0; + struct timer_sp804 sp804; void __iomem *base; - int irq; - const char *name = of_get_property(np, "compatible", NULL); struct clk *clk; base = of_iomap(np, 0); @@ -292,14 +311,22 @@ static void __init integrator_cp_of_init(struct device_node *np) if (init_count == 2 || !of_device_is_available(np)) goto err; - if (!init_count) - __sp804_clocksource_and_sched_clock_init(base, name, clk, 0); - else { - irq = irq_of_parse_and_map(np, 0); - if (irq <= 0) + sp804.name = of_get_property(np, "compatible", NULL); + sp804.width = 32; + + if (!init_count) { + sp804.clocksource_base = base; + sp804.clocksource_clk = clk; + + __sp804_clocksource_and_sched_clock_init(&sp804, false); + } else { + sp804.clockevent_base = base; + sp804.clockevent_clk = clk; + sp804.irq = irq_of_parse_and_map(np, 0); + if (sp804.irq <= 0) goto err; - __sp804_clockevents_init(base, irq, clk, name); + __sp804_clockevents_init(&sp804); } init_count++; diff --git a/include/clocksource/timer-sp804.h b/include/clocksource/timer-sp804.h index 1f8a1ca..928091b 100644 --- a/include/clocksource/timer-sp804.h +++ b/include/clocksource/timer-sp804.h @@ -3,26 +3,54 @@ struct clk; -void __sp804_clocksource_and_sched_clock_init(void __iomem *, - const char *, struct clk *, int); -void __sp804_clockevents_init(void __iomem *, unsigned int, - struct clk *, const char *); +struct timer_sp804 { + void __iomem *clockevent_base; + void __iomem *clocksource_base; + const char *name; + struct clk *clockevent_clk; + struct clk *clocksource_clk; + unsigned int irq; + unsigned int width; +}; + +void __sp804_clocksource_and_sched_clock_init(struct timer_sp804 *sp804, bool); +void __sp804_clockevents_init(struct timer_sp804 *sp804); void sp804_timer_disable(void __iomem *); static inline void sp804_clocksource_init(void __iomem *base, const char *name) { - __sp804_clocksource_and_sched_clock_init(base, name, NULL, 0); + struct timer_sp804 sp804 = { + .clocksource_base = base, + .name = name, + .clocksource_clk = NULL, + .width = 32, + }; + + __sp804_clocksource_and_sched_clock_init(&sp804, false); } static inline void sp804_clocksource_and_sched_clock_init(void __iomem *base, const char *name) { - __sp804_clocksource_and_sched_clock_init(base, name, NULL, 1); + struct timer_sp804 sp804 = { + .clocksource_base = base, + .name = name, + .clocksource_clk = NULL, + .width = 32, + }; + + __sp804_clocksource_and_sched_clock_init(&sp804, true); } static inline void sp804_clockevents_init(void __iomem *base, unsigned int irq, const char *name) { - __sp804_clockevents_init(base, irq, NULL, name); + struct timer_sp804 sp804 = { + .clockevent_base = base, + .name = name, + .clockevent_clk = NULL, + .width = 32, + }; + __sp804_clockevents_init(&sp804); } #endif