From patchwork Thu Apr 7 02:51:18 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 8768231 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 9E4E89F3D1 for ; Thu, 7 Apr 2016 02:55:36 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C926D201C7 for ; Thu, 7 Apr 2016 02:55:35 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E704A201BC for ; Thu, 7 Apr 2016 02:55:34 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ao05E-0002GS-5W; Thu, 07 Apr 2016 02:54:12 +0000 Received: from mail-pf0-x229.google.com ([2607:f8b0:400e:c00::229]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ao04m-0001pu-OR for linux-arm-kernel@lists.infradead.org; Thu, 07 Apr 2016 02:53:57 +0000 Received: by mail-pf0-x229.google.com with SMTP id 184so46156972pff.0 for ; Wed, 06 Apr 2016 19:53:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=JPMkKb/ZNkjTmppkRAdYf23PWZMo/NFHNJm5LC5Eug8=; b=KfVwSQPQ5f3KOA4afVdND4MGO49xZ7XIqqVVbUFPWdXsarUZ6AJP8VoAX/V+HcgSWU FFtdPPHxQUgei3CjpImJI3/ikpM7UsBb53z8c3nOANH2fh1v+T7d5ujZIRJfSpdUGe0t JTOQ/RA5+KIhQIZtal//9KZJAfQCOouGrK0XU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=JPMkKb/ZNkjTmppkRAdYf23PWZMo/NFHNJm5LC5Eug8=; b=lOT7Vp3doS6xpyi05pVGaNzSxcZGyHpGKdpOqft5hftbooBhW60kAvRe5oPTwdyYa4 K5hUotqE2PciqbaJC/RwbPPbTwgEnUkmM/6+O1tBSGndUNe6G3NOHJUtYIOCCi+Xk/Li Z4v8DlLYrWywrWOLUFsSMae4FCCjs6XR6i9nY0vMsegUWResgzn4T5EfmighS63MF6bw OLqz0kKUKG8ItS6iY51Au1WQ1AdErJ6PFMHMtaeFwDGGrgF40mr2F9sh41rBZFz3s7aw Z7OEUp9EO3KnDL0bicxh5huhqTT4OyMnSp3Zl6ncu4dnslJ+HQwXYCognystcFM91gla ptuQ== X-Gm-Message-State: AD7BkJJh9Kb8m+yJbgDxu6wGivTPWdEwc8rwo/c30TwcUnF7+ln/p/sEx+HwQSxGUMhHktps X-Received: by 10.98.76.194 with SMTP id e63mr1104790pfj.89.1459997604331; Wed, 06 Apr 2016 19:53:24 -0700 (PDT) Received: from zcy-ubuntu.spreadtrum.com ([175.111.195.49]) by smtp.gmail.com with ESMTPSA id xa4sm7829736pab.26.2016.04.06.19.53.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 06 Apr 2016 19:53:23 -0700 (PDT) From: Chunyan Zhang To: mathieu.poirier@linaro.org, alexander.shishkin@linux.intel.com Subject: [PATCH V5 3/4] coresight-stm: Bindings for System Trace Macrocell Date: Thu, 7 Apr 2016 10:51:18 +0800 Message-Id: <1459997479-19431-4-git-send-email-zhang.chunyan@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1459997479-19431-1-git-send-email-zhang.chunyan@linaro.org> References: <1459997479-19431-1-git-send-email-zhang.chunyan@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160406_195345_199777_C245847C X-CRM114-Status: GOOD ( 11.28 ) X-Spam-Score: -2.7 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: al.grant@arm.com, Michael.Williams@arm.com, linux-doc@vger.kernel.org, zhang.lyra@gmail.com, linux-kernel@vger.kernel.org, tor@ti.com, mike.leach@arm.com, linux-api@vger.kernel.org, pratikp@codeaurora.org, nicolas.guion@st.com, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Mathieu Poirier The System Trace Macrocell (STM) is an IP block falling under the CoreSight umbrella. It's main purpose it so expose stimulus channels to any system component for the purpose of information logging. Bindings for this IP block adds a couple of items to the current mandatory definition for CoreSight components. Signed-off-by: Mathieu Poirier Acked-by: Rob Herring Signed-off-by: Chunyan Zhang --- .../devicetree/bindings/arm/coresight.txt | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt index 62938eb..93147c0c 100644 --- a/Documentation/devicetree/bindings/arm/coresight.txt +++ b/Documentation/devicetree/bindings/arm/coresight.txt @@ -19,6 +19,7 @@ its hardware characteristcs. - "arm,coresight-etm3x", "arm,primecell"; - "arm,coresight-etm4x", "arm,primecell"; - "qcom,coresight-replicator1x", "arm,primecell"; + - "arm,coresight-stm", "arm,primecell"; [1] * reg: physical base address and length of the register set(s) of the component. @@ -36,6 +37,14 @@ its hardware characteristcs. layout using the generic DT graph presentation found in "bindings/graph.txt". +* Additional required properties for System Trace Macrocells (STM): + * reg: along with the physical base address and length of the register + set as described above, another entry is required to describe the + mapping of the extended stimulus port area. + + * reg-names: the only acceptable values are "stm-base" and + "stm-stimulus-base", each corresponding to the areas defined in "reg". + * Required properties for devices that don't show up on the AMBA bus, such as non-configurable replicators: @@ -202,3 +211,22 @@ Example: }; }; }; + +4. STM + stm@20100000 { + compatible = "arm,coresight-stm", "arm,primecell"; + reg = <0 0x20100000 0 0x1000>, + <0 0x28000000 0 0x180000>; + reg-names = "stm-base", "stm-stimulus-base"; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + port { + stm_out_port: endpoint { + remote-endpoint = <&main_funnel_in_port2>; + }; + }; + }; + +[1]. There is currently two version of STM: STM32 and STM500. Both +have the same HW interface and as such don't need an explicit binding name.