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Fri, 08 Apr 2016 13:25:13 +0900 (KST) From: Chanwoo Choi To: myungjoo.ham@samsung.com, kyungmin.park@samsung.com, k.kozlowski@samsung.com, kgene@kernel.org Subject: [PATCH v8 13/20] ARM: dts: Add bus nodes using VDD_INT for Exynos3250 Date: Fri, 08 Apr 2016 13:25:02 +0900 Message-id: <1460089509-16260-14-git-send-email-cw00.choi@samsung.com> X-Mailer: git-send-email 1.8.0 In-reply-to: <1460089509-16260-1-git-send-email-cw00.choi@samsung.com> References: <1460089509-16260-1-git-send-email-cw00.choi@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrAIsWRmVeSWpSXmKPExsWyRsSkRHeVEXu4waqLrBbXvzxntZh/5Byr Rf+bhawW516tZLSYdH8Ci8XrF4YW/Y9fM1ucbXrDbrHp8TVWi8u75rBZfO49wmgx4/w+Jot1 G2+xW9y+zGvx8sgPRoul1y8yWdxuXMFmMWH6WhaLM6cvsVq07j3CbtG2+gOrg6jHmnlrGD1a mnvYPC739TJ53LpT77Fz1l12j5XLv7B5bFrVyeaxeUm9x79j7B5brrazePRtWcXo8XmTXABP FJdNSmpOZllqkb5dAlfG9PZzrAVrlSumP/rF2sD4TaqLkZNDQsBE4vOddewQtpjEhXvr2boY uTiEBFYwSjx63sYEUzTn9BNWiMQsRomjX6ZAVX1hlPi+ewErSBWbgJbE/hc32EBsEYEUiccP T4IVMQscYZaYuvEG0CgODmEBP4kjv/VBalgEVCWWz+5mAbF5BdwkWn9NYoTYJifxYc8jsJM4 geKTr0xiBrGFBFwlbmyezgwyU0JgB4fEhK6jzBCDBCS+TT7EAjJfQkBWYtMBZog5khIHV9xg mcAovICRYRWjaGpBckFxUnqRsV5xYm5xaV66XnJ+7iZGYMSe/vesfwfj3QPWhxgFOBiVeHgv vGcLF2JNLCuuzD3EaAq0YSKzlGhyPjAt5JXEGxqbGVmYmpgaG5lbmimJ8y6U+hksJJCeWJKa nZpakFoUX1Sak1p8iJGJg1OqgTGFVfbh/N3LJ/1+5p+/k/uVuLZ0rmIQ79UJ9n9evc+Y+CCl tmJrxO+dWblMd6cuyvWJVjVm9ZZfIXA99vS2DMVGvZtPrP1vKS5aeSSjeZF6xUoOe5HNDMn/ 23/dD/z8cMn34E2PrmvYXxFzO9f7W67CN2PihGOym/rcX1xeNtfr/IbtBqIT4u4rsRRnJBpq MRcVJwIAEB85Y9MCAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFuplleLIzCtJLcpLzFFi42I5/e+xoO5KI/Zwg5V9FhbXvzxntZh/5Byr Rf+bhawW516tZLSYdH8Ci8XrF4YW/Y9fM1ucbXrDbrHp8TVWi8u75rBZfO49wmgx4/w+Jot1 G2+xW9y+zGvx8sgPRoul1y8yWdxuXMFmMWH6WhaLM6cvsVq07j3CbtG2+gOrg6jHmnlrGD1a mnvYPC739TJ53LpT77Fz1l12j5XLv7B5bFrVyeaxeUm9x79j7B5brrazePRtWcXo8XmTXABP VAOjTUZqYkpqkUJqXnJ+SmZeuq2Sd3C8c7ypmYGhrqGlhbmSQl5ibqqtkotPgK5bZg7Qr0oK ZYk5pUChgMTiYiV9O0wTQkPcdC1gGiN0fUOC4HqMDNBAwhrGjOnt51gL1ipXTH/0i7WB8ZtU FyMnh4SAicSc009YIWwxiQv31rN1MXJxCAnMYpQ4+mUKlPOFUeL77gVgVWwCWhL7X9xgA7FF BFIkHj88CVbELHCEWWLqxhtMXYwcHMICfhJHfuuD1LAIqEosn93NAmLzCrhJtP6axAixTU7i w55H7CA2J1B88pVJzCC2kICrxI3N05knMPIuYGRYxSiRWpBcUJyUnmuYl1quV5yYW1yal66X nJ+7iRGcFJ5J7WA8uMv9EKMAB6MSD++F92zhQqyJZcWVuYcYJTiYlUR4XfXZw4V4UxIrq1KL 8uOLSnNSiw8xmgIdNpFZSjQ5H5iw8kriDY1NzIwsjcwNLYyMzZXEeR//XxcmJJCeWJKanZpa kFoE08fEwSnVwBjr353iGrcmQdiGbdUMecbG2RuMJv/fJaMa9krlq6LjX6P9Jz4FP/Hdw/ZC gs3jwTvWKZmrfO1nP0mxOOe2fS7vX5HTq7TyxM+rVlhetrzUrpQyz4zB6iOP9YP36+LqDxkU fXruNs3xzYGE53f0tG6fCV+fsjCv4IPdYw4LK7XHT283bPnCF6rEUpyRaKjFXFScCAAftStI IAMAAA== DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160407_212549_665131_50F359C8 X-CRM114-Status: GOOD ( 10.36 ) X-Spam-Score: -7.9 (-------) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, inki.dae@samsung.com, linux-samsung-soc@vger.kernel.org, linux@arm.linux.org.uk, cw00.choi@samsung.com, pawel.moll@arm.com, ijc+devicetree@hellion.org.uk, linux.amoon@gmail.com, linux-pm@vger.kernel.org, rjw@rjwysocki.net, linux-kernel@vger.kernel.org, m.reichl@fivetechno.de, tjakobi@math.uni-bielefeld.de, devicetree@vger.kernel.org, robh+dt@kernel.org, galak@codeaurora.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds the bus nodes using VDD_INT for Exynos3250 SoC. Exynos3250 has following AXI buses to translate data between DRAM and sub-blocks. Following list specifies the detailed relation between DRAM and sub-blocks: - ACLK400 clock for MCUISP - ACLK266 clock for ISP - ACLK200 clock for FSYS - ACLK160 clock for LCD0 - ACLK100 clock for PERIL - GDL clock for LEFTBUS - GDR clock for RIGHTBUS - SCLK_MFC clock for MFC Signed-off-by: Chanwoo Choi Reviewed-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos3250.dtsi | 147 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 147 insertions(+) diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi index 1ae72c4fa55e..b5157492a422 100644 --- a/arch/arm/boot/dts/exynos3250.dtsi +++ b/arch/arm/boot/dts/exynos3250.dtsi @@ -722,6 +722,153 @@ opp-microvolt = <875000>; }; }; + + bus_leftbus: bus_leftbus { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_DIV_GDL>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_rightbus: bus_rightbus { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_DIV_GDR>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_lcd0: bus_lcd0 { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_DIV_ACLK_160>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_fsys: bus_fsys { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_DIV_ACLK_200>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_mcuisp: bus_mcuisp { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>; + clock-names = "bus"; + operating-points-v2 = <&bus_mcuisp_opp_table>; + status = "disabled"; + }; + + bus_isp: bus_isp { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_DIV_ACLK_266>; + clock-names = "bus"; + operating-points-v2 = <&bus_isp_opp_table>; + status = "disabled"; + }; + + bus_peril: bus_peril { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_DIV_ACLK_100>; + clock-names = "bus"; + operating-points-v2 = <&bus_peril_opp_table>; + status = "disabled"; + }; + + bus_mfc: bus_mfc { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_SCLK_MFC>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_leftbus_opp_table: opp_table2 { + compatible = "operating-points-v2"; + opp-shared; + + opp@50000000 { + opp-hz = /bits/ 64 <50000000>; + opp-microvolt = <900000>; + }; + opp@80000000 { + opp-hz = /bits/ 64 <80000000>; + opp-microvolt = <900000>; + }; + opp@100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <1000000>; + }; + opp@134000000 { + opp-hz = /bits/ 64 <134000000>; + opp-microvolt = <1000000>; + }; + opp@200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <1000000>; + }; + }; + + bus_mcuisp_opp_table: opp_table3 { + compatible = "operating-points-v2"; + opp-shared; + + opp@50000000 { + opp-hz = /bits/ 64 <50000000>; + }; + opp@80000000 { + opp-hz = /bits/ 64 <80000000>; + }; + opp@100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + opp@200000000 { + opp-hz = /bits/ 64 <200000000>; + }; + opp@400000000 { + opp-hz = /bits/ 64 <400000000>; + }; + }; + + bus_isp_opp_table: opp_table4 { + compatible = "operating-points-v2"; + opp-shared; + + opp@50000000 { + opp-hz = /bits/ 64 <50000000>; + }; + opp@80000000 { + opp-hz = /bits/ 64 <80000000>; + }; + opp@100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + opp@200000000 { + opp-hz = /bits/ 64 <200000000>; + }; + opp@300000000 { + opp-hz = /bits/ 64 <300000000>; + }; + }; + + bus_peril_opp_table: opp_table5 { + compatible = "operating-points-v2"; + opp-shared; + + opp@50000000 { + opp-hz = /bits/ 64 <50000000>; + }; + opp@80000000 { + opp-hz = /bits/ 64 <80000000>; + }; + opp@100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + }; }; };