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Fri, 08 Apr 2016 13:25:14 +0900 (KST) From: Chanwoo Choi To: myungjoo.ham@samsung.com, kyungmin.park@samsung.com, k.kozlowski@samsung.com, kgene@kernel.org Subject: [PATCH v8 15/20] ARM: dts: Add bus nodes using VDD_INT for Exynos4x12 Date: Fri, 08 Apr 2016 13:25:04 +0900 Message-id: <1460089509-16260-16-git-send-email-cw00.choi@samsung.com> X-Mailer: git-send-email 1.8.0 In-reply-to: <1460089509-16260-1-git-send-email-cw00.choi@samsung.com> References: <1460089509-16260-1-git-send-email-cw00.choi@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAAzWSa0iTURjHPXuvLoWXeTuJGgz9ssi8d0IpIbI3IrMMpAvo0pcpuimbSn3S Ll7zLqZI5gxFnZo5l9jNbI5Kl6bN5vBS1Lp4WWhOKiWsudG3/3nOn9/vw/PQmGAY96bTZNmc XCbOEJJ8vNs9LHufKoRKCGrY3oNmNr4RqFk3QaBKSwuBJpY7Aar5UIWjlcVgVGlewdD4NQuF 1GYjgQyPbpPIWq4DqOHNEA/d65ul0JzBFS3pfgPUNjPFQ3NXO0hUVd+Do9f6twQqeKqjUGHX GhHtwXbf6QbsjetlJGuoKOexs/N57MPGBYrtbN8gWbWqhGT7W/PY7RcUq3lXhLMVGhVgrWq/ OJfz/KgULiMtl5PvP5TET53/rqey1n0ulz2eJPNBsVcpcKYhEwYLLFaeI3vCyfe9ZCng0wKm A8A/xib8f6lwJJ9yfDQCWDT2F3M8NgAs7Gkhd1okI4LPFk327M6kQPPHUTsKY3QYrOsz2R1u TCxcN7RjOxlnAuByvwaUApp2ZWLgr5nDDpsfXHvyidrJzrZx7XSNvS5gjkJTf71dDBkNDQcG lLiDw8CftVp8hwMZX6gexhyc3fB5hwmvAm5K4KQCHlxWcpbikkQeGqgQSxU5MklgcqZUDWyL 1W9/rRwEC8ORWsDQQOjiOrlKJggIca7iilQLwm2GaszbIznTdguy7MTg0IgQFB4WHhpy4GCE 0Mu1xXszXsBIxNlcOsdlcfJEeU4Gp9ACHu3snQ/a9uoHx5bijcW9nk3Lo8drfH0su84qz8We 0bd/MUxiq1tD1FCA/2f/SEnziZfzuVFTK7cuKF4Nap39I4o0iXPp40zJj/uUNO602anuVHUM qwoKqCgRVUmdjkwrW7m7sKtn03DSyF0UQ8JpfKNzq2hz4sGxmyMwesIqTPITJQhxRao4WITJ FeJ/P0O8gtMCAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFuplleLIzCtJLcpLzFFi42I5/e+xoO4qI/ZwgzO7xSyuf3nOajH/yDlW i/43C1ktzr1ayWgx6f4EFovXLwwt+h+/ZrY42/SG3WLT42usFpd3zWGz+Nx7hNFixvl9TBbr Nt5it7h9mdfi5ZEfjBZLr19ksrjduILNYsL0tSwWZ05fYrVo3XuE3aJt9QdWB1GPNfPWMHq0 NPeweVzu62XyuHWn3mPnrLvsHiuXf2Hz2LSqk81j85J6j3/H2D22XG1n8ejbsorR4/MmuQCe qAZGm4zUxJTUIoXUvOT8lMy8dFsl7+B453hTMwNDXUNLC3MlhbzE3FRbJRefAF23zBygX5UU yhJzSoFCAYnFxUr6dpgmhIa46VrANEbo+oYEwfUYGaCBhDWMGXfenmYv+CRT0bP7AlsDY4d4 FyMnh4SAiUTb4QZ2CFtM4sK99WxdjFwcQgKzGCXaT/1nhnC+MEq0rV3IBlLFJqAlsf/FDTBb RCBF4vHDk2AdzAJHmCWmbrzBBJIQFvCT+HR5OTOIzSKgKvFq8xbGLkYODl4BN4nv1+0htslJ fNjzCGwzJ1B48pVJYOVCAq4SNzZPZ57AyLuAkWEVo0RqQXJBcVJ6rmFearlecWJucWleul5y fu4mRnBSeCa1g/HgLvdDjAIcjEo8vBfes4ULsSaWFVfmHmKU4GBWEuF11WcPF+JNSaysSi3K jy8qzUktPsRoCnTXRGYp0eR8YMLKK4k3NDYxM7I0Mje0MDI2VxLnffx/XZiQQHpiSWp2ampB ahFMHxMHp1QD46zFfgUhG++/Tqv+l3Q8OI/595nLBp9rvxz9Oi1D84HuvAOR27lM2PLeXWOY wyN/b1urzz1HLRPvHyz/j+xw3Whv+cNqe2JqvFul+d5TxS9Mk9k3Bydt183U0FzY/evnpIf2 O7aGn/fcsGeettkxAzVxq3CROYrs69e6+wS+PhqepTohYcdCRiWW4oxEQy3mouJEAMR/9YYg AwAA DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160407_212541_740245_79ED2EC2 X-CRM114-Status: GOOD ( 10.61 ) X-Spam-Score: -7.9 (-------) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, inki.dae@samsung.com, linux-samsung-soc@vger.kernel.org, linux@arm.linux.org.uk, cw00.choi@samsung.com, pawel.moll@arm.com, ijc+devicetree@hellion.org.uk, linux.amoon@gmail.com, linux-pm@vger.kernel.org, rjw@rjwysocki.net, linux-kernel@vger.kernel.org, m.reichl@fivetechno.de, tjakobi@math.uni-bielefeld.de, devicetree@vger.kernel.org, robh+dt@kernel.org, galak@codeaurora.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds the bus nodes using VDD_INT for Exynos4x12 SoC. Exynos4x12 has the following AXI buses to translate data between DRAM and sub-blocks. Following list specifies the detailed relation between DRAM and sub-blocks: - ACLK100 clock for PERIL/PERIR/MFC(PCLK) - ACLK160 clock for CAM/TV/LCD : The minimum clock of ACLK160 should be over 160MHz. When drop the clock under 160MHz, show the broken image. - ACLK133 clock for FSYS - GDL clock for LEFTBUS - GDR clock for RIGHTBUS - SCLK_MFC clock for MFC Signed-off-by: Chanwoo Choi Reviewed-by: Krzysztof Kozlowski [m.reichl and linux.amoon: Tested it on exynos4412-odroidu3 board] Tested-by: Markus Reichl Tested-by: Anand Moon --- arch/arm/boot/dts/exynos4x12.dtsi | 106 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 106 insertions(+) diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi index 99a0f4ca3d47..e5173107ed44 100644 --- a/arch/arm/boot/dts/exynos4x12.dtsi +++ b/arch/arm/boot/dts/exynos4x12.dtsi @@ -349,6 +349,112 @@ opp-hz = /bits/ 64 <267000000>; }; }; + + bus_leftbus: bus_leftbus { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DIV_GDL>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_rightbus: bus_rightbus { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DIV_GDR>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_display: bus_display { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_ACLK160>; + clock-names = "bus"; + operating-points-v2 = <&bus_display_opp_table>; + status = "disabled"; + }; + + bus_fsys: bus_fsys { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_ACLK133>; + clock-names = "bus"; + operating-points-v2 = <&bus_fsys_opp_table>; + status = "disabled"; + }; + + bus_peri: bus_peri { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_ACLK100>; + clock-names = "bus"; + operating-points-v2 = <&bus_peri_opp_table>; + status = "disabled"; + }; + + bus_mfc: bus_mfc { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_SCLK_MFC>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_leftbus_opp_table: opp_table3 { + compatible = "operating-points-v2"; + opp-shared; + + opp@100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <900000>; + }; + opp@134000000 { + opp-hz = /bits/ 64 <134000000>; + opp-microvolt = <925000>; + }; + opp@160000000 { + opp-hz = /bits/ 64 <160000000>; + opp-microvolt = <950000>; + }; + opp@200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <1000000>; + }; + }; + + bus_display_opp_table: opp_table4 { + compatible = "operating-points-v2"; + opp-shared; + + opp@160000000 { + opp-hz = /bits/ 64 <160000000>; + }; + opp@200000000 { + opp-hz = /bits/ 64 <200000000>; + }; + }; + + bus_fsys_opp_table: opp_table5 { + compatible = "operating-points-v2"; + opp-shared; + + opp@100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + opp@134000000 { + opp-hz = /bits/ 64 <134000000>; + }; + }; + + bus_peri_opp_table: opp_table6 { + compatible = "operating-points-v2"; + opp-shared; + + opp@50000000 { + opp-hz = /bits/ 64 <50000000>; + }; + opp@100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + }; }; &combiner {