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Mon, 11 Apr 2016 12:58:02 +0900 (KST) From: Chanwoo Choi To: myungjoo.ham@samsung.com, kyungmin.park@samsung.com, k.kozlowski@samsung.com, kgene@kernel.org, s.nawrocki@samsung.com, tomasz.figa@gmail.com Subject: [PATCH v9 20/20] ARM: dts: Add support of bus frequency for exynos4412-trats/odroidu3 Date: Mon, 11 Apr 2016 12:57:58 +0900 Message-id: <1460347078-15175-21-git-send-email-cw00.choi@samsung.com> X-Mailer: git-send-email 1.8.0 In-reply-to: <1460347078-15175-1-git-send-email-cw00.choi@samsung.com> References: <1460347078-15175-1-git-send-email-cw00.choi@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrFIsWRmVeSWpSXmKPExsWyRsSkQPeUAne4wc/7lhbXvzxntZh/5Byr Rf+bhawW516tZLSYdH8Ci8XrF4YW/Y9fM1ucbXrDbrHp8TVWi8u75rBZfO49wmgx4/w+Jot1 G2+xW9y+zGvx8sgPRoul1y8yWdxuXMFmMWH6WhaLM6cvsVq07j3CbnH4TTurRdvqD6wWq3b9 YXQQ91gzbw2jR0tzD5vH5b5eJo9bd+o9ds66y+6xcvkXNo9NqzrZPDYvqff4d4zdY8vVdhaP vi2rGD0+b5IL4InisklJzcksSy3St0vgyljz8x9TwVOxiiu7TrE2MJ4R6mLk5JAQMJHYsWYL O4QtJnHh3nq2LkYuDiGBFYwSM588Z4Qpmv3nICtEYhajxL/2FkYI5wujxNNdN5hAqtgEtCT2 v7gB1i4iMJVR4vOpNhYQh1ngCLPE1I0gVRwcwgIJEsuP6oA0sAioSmx+dxNsN6+Am8Spy11Q d8hJfNjzCMzmBIp/Wt/OCtIqJOAq8exzHchICYEjHBL9E96yQcwRkPg2+RALSI2EgKzEpgPM EGMkJQ6uuMEygVF4ASPDKkbR1ILkguKk9CJjveLE3OLSvHS95PzcTYzAKD7971n/Dsa7B6wP MQpwMCrx8Dpc4woXYk0sK67MPcRoCrRhIrOUaHI+MFXklcQbGpsZWZiamBobmVuaKYnzLpT6 GSwkkJ5YkpqdmlqQWhRfVJqTWnyIkYmDU6qBMUab2Xf9rFvFC+KtCth2vL4iUaN76D3TqVqN X1tmdHzav2tHf9wFrrUiaqHWmQ/XBV3oMdOeo3ri/ab1uUkH9uYz+rScKxMPOKgyr5fN5+2Z tTMuzSk+aMdu4sX0X+R24oT9B2LmW6lpCam+Mdg8U0VZS3lbebX6m5qbJ9tmWPi81y47aRR+ UImlOCPRUIu5qDgRAGWMzg/dAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprOKsWRmVeSWpSXmKPExsVy+t9jQd1TCtzhBv9eGllc//Kc1WL+kXOs Fv1vFrJanHu1ktFi0v0JLBavXxha9D9+zWxxtukNu8Wmx9dYLS7vmsNm8bn3CKPFjPP7mCzW bbzFbnH7Mq/FyyM/GC2WXr/IZHG7cQWbxYTpa1kszpy+xGrRuvcIu8XhN+2sFm2rP7BarNr1 h9FB3GPNvDWMHi3NPWwel/t6mTxu3an32DnrLrvHyuVf2Dw2repk89i8pN7j3zF2jy1X21k8 +rasYvT4vEkugCeqgdEmIzUxJbVIITUvOT8lMy/dVsk7ON453tTMwFDX0NLCXEkhLzE31VbJ xSdA1y0zB+hrJYWyxJxSoFBAYnGxkr4dpgmhIW66FjCNEbq+IUFwPUYGaCBhDWPGmp//mAqe ilVc2XWKtYHxjFAXIyeHhICJxOw/B1khbDGJC/fWs3UxcnEICcxilPjX3sII4XxhlHi66wYT SBWbgJbE/hc3wKpEBKYySnw+1cYC4jALHGGWmLoRpIqDQ1ggQWL5UR2QBhYBVYnN726yg9i8 Am4Spy53sUOsk5P4sOcRmM0JFP+0vp0VpFVIwFXi2ee6CYy8CxgZVjFKpBYkFxQnpeca5aWW 6xUn5haX5qXrJefnbmIEJ4pn0jsYD+9yP8QowMGoxMP74jJXuBBrYllxZe4hRgkOZiUR3gey 3OFCvCmJlVWpRfnxRaU5qcWHGE2B7prILCWanA9MYnkl8YbGJmZGlkbmhhZGxuZK4ryP/68L ExJITyxJzU5NLUgtgulj4uCUamB0eKrMMWnfXZdsQ/m1u2atjduhFZLrtEsvezdXycKJIfuX bpphvPfG4kNv363xiIjP+svP8uVU2+H4ZaVlk5V0lVR/tJnfYo7Pn/nwwieBis33XGVjDTZc Whd1btH7na/NMztDBLn1RK3ldolmG0j6H+tVY1y7X6V35/lZC54Le++deqnGcMd9JZbijERD Leai4kQARqageCoDAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160410_205849_457415_6CD242DF X-CRM114-Status: GOOD ( 11.17 ) X-Spam-Score: -7.9 (-------) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, inki.dae@samsung.com, linux-samsung-soc@vger.kernel.org, linux@arm.linux.org.uk, cw00.choi@samsung.com, pawel.moll@arm.com, ijc+devicetree@hellion.org.uk, linux.amoon@gmail.com, linux-pm@vger.kernel.org, rjw@rjwysocki.net, linux-kernel@vger.kernel.org, m.reichl@fivetechno.de, tjakobi@math.uni-bielefeld.de, devicetree@vger.kernel.org, robh+dt@kernel.org, galak@codeaurora.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-3.4 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RDNS_NONE,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP THis patch adds the bus device tree nodes for both MIF (Memory) and INT (Internal) block to enable the bus frequency. The DMC bus is parent device in MIF block using VDD_MIF and the LEFTBUS bus is parent device in INT block using VDD_INT. Signed-off-by: Chanwoo Choi Reviewed-by: Krzysztof Kozlowski [m.reichl and linux.amoon: Tested it on exynos4412-odroidu3 board] Tested-by: Markus Reichl Tested-by: Anand Moon --- arch/arm/boot/dts/exynos4412-odroid-common.dtsi | 47 +++++++++++++++++++++++++ arch/arm/boot/dts/exynos4412-trats2.dts | 47 +++++++++++++++++++++++++ 2 files changed, 94 insertions(+) diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi index b4983cbc4f8c..2015f10071f9 100644 --- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi +++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi @@ -109,6 +109,53 @@ }; }; +&bus_dmc { + devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>; + vdd-supply = <&buck1_reg>; + status = "okay"; +}; + +&bus_acp { + devfreq = <&bus_dmc>; + status = "okay"; +}; + +&bus_c2c { + devfreq = <&bus_dmc>; + status = "okay"; +}; + +&bus_leftbus { + devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>; + vdd-supply = <&buck3_reg>; + status = "okay"; +}; + +&bus_rightbus { + devfreq = <&bus_leftbus>; + status = "okay"; +}; + +&bus_display { + devfreq = <&bus_leftbus>; + status = "okay"; +}; + +&bus_fsys { + devfreq = <&bus_leftbus>; + status = "okay"; +}; + +&bus_peri { + devfreq = <&bus_leftbus>; + status = "okay"; +}; + +&bus_mfc { + devfreq = <&bus_leftbus>; + status = "okay"; +}; + &cpu0 { cpu0-supply = <&buck2_reg>; }; diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts b/arch/arm/boot/dts/exynos4412-trats2.dts index dce3cebe0606..9f3fb9a7f5f4 100644 --- a/arch/arm/boot/dts/exynos4412-trats2.dts +++ b/arch/arm/boot/dts/exynos4412-trats2.dts @@ -289,6 +289,53 @@ status = "okay"; }; +&bus_dmc { + devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>; + vdd-supply = <&buck1_reg>; + status = "okay"; +}; + +&bus_acp { + devfreq = <&bus_dmc>; + status = "okay"; +}; + +&bus_c2c { + devfreq = <&bus_dmc>; + status = "okay"; +}; + +&bus_leftbus { + devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>; + vdd-supply = <&buck3_reg>; + status = "okay"; +}; + +&bus_rightbus { + devfreq = <&bus_leftbus>; + status = "okay"; +}; + +&bus_display { + devfreq = <&bus_leftbus>; + status = "okay"; +}; + +&bus_fsys { + devfreq = <&bus_leftbus>; + status = "okay"; +}; + +&bus_peri { + devfreq = <&bus_leftbus>; + status = "okay"; +}; + +&bus_mfc { + devfreq = <&bus_leftbus>; + status = "okay"; +}; + &cpu0 { cpu0-supply = <&buck2_reg>; };