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Tue, 12 Apr 2016 20:07:10 +0900 (KST) From: Alim Akhtar To: linux-arm-kernel@lists.infradead.org, s.nawrocki@samsung.com Subject: [PATCH] clk: samsung: exynos7: Enable clocks for CMU_CCORE and CMU_FSYS0 blocks Date: Tue, 12 Apr 2016 16:37:23 +0530 Message-id: <1460459243-27120-1-git-send-email-alim.akhtar@samsung.com> X-Mailer: git-send-email 1.7.10.4 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrCLMWRmVeSWpSXmKPExsWyRsSkTffeNZ5wgxMntSxevzC02PT4GqvF x557rBaXd81hs5hxfh+TxcVTrhaH37SzWvw4081i0bGM0WLVrj+MDlwe72+0sntc7utl8tg5 6y67x+Yl9R59W1YxenzeJBfAFsVlk5Kak1mWWqRvl8CV0XXyDVPBfq6KU8s/sDUwvuXoYuTk kBAwkfh9eR0ThC0mceHeerYuRi4OIYEVjBIzVm5jhym6M3kCVGIWo8SBY89ZIJyfjBLbDl5m A6liE9CWuDt9C9AoDg4RAQeJ062CIDXMArcYJU5cXMAKUiMsECXx5tR1sKksAqoS5zfuAFvN K+AucebJTUaIbYoS3c8gtkkIzGOXOLvnIiNEg4DEt8mHWEAWSAjISmw6wAxRLylxcMUNlgmM ggsYGVYxiqYWJBcUJ6UXGesVJ+YWl+al6yXn525iBAb26X/P+ncw3j1gfYhRgINRiYf3oTNP uBBrYllxZe4hRlOgDROZpUST84Hxk1cSb2hsZmRhamJqbGRuaaYkzrtQ6mewkEB6Yklqdmpq QWpRfFFpTmrxIUYmDk6pBsaT0ydnBE/7XNkqtvT80aqLyyz55/0V21Shf1Dw06/Vz16aJ+nW Nq+z/falljsvJSdiRrDiDkaWpIa8fKU3rqm3brKFrIzZal+WkZJtKz5nxec32VG1TKfv/W54 ZuyWraXw63pZkOTZVN7TZw/JVTstT3r9wI39DWOD8pL7R6xSJ5hYnLfi+azEUpyRaKjFXFSc CACJCFZcZwIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrIIsWRmVeSWpSXmKPExsVy+t9jQd1713jCDe51qVm8fmFosenxNVaL jz33WC0u75rDZjHj/D4mi4unXC0Ov2lntfhxppvFomMZo8WqXX8YHbg83t9oZfe43NfL5LFz 1l12j81L6j36tqxi9Pi8SS6ALaqB0SYjNTEltUghNS85PyUzL91WyTs43jne1MzAUNfQ0sJc SSEvMTfVVsnFJ0DXLTMH6C4lhbLEnFKgUEBicbGSvh2mCaEhbroWMI0Rur4hQXA9RgZoIGEd Y0bXyTdMBfu5Kk4t/8DWwPiWo4uRk0NCwETizuQJbBC2mMSFe+uBbC4OIYFZjBIHjj1ngXB+ MkpsO3gZrIpNQFvi7vQtTF2MHBwiAg4Sp1sFQWqYBW4xSpy4uIAVpEZYIErizanr7CA2i4Cq xPmNO5hAbF4Bd4kzT24yQmxTlOh+NoFtAiP3AkaGVYwSqQXJBcVJ6bmGeanlesWJucWleel6 yfm5mxjB0fNMagfjwV3uhxgFOBiVeHgDl/GEC7EmlhVX5h5ilOBgVhLhbb8MFOJNSaysSi3K jy8qzUktPsRoCnTARGYp0eR8YGTnlcQbGpuYGVkamVkYmZibK4nzPv6/LkxIID2xJDU7NbUg tQimj4mDU6qB0XnL9rAXZo9viwhbv5EWCvOfMVntSvSn9XoilcXiegY3dXk8FmlGP+j+e0aE NZNl+U2J1lMim41nb/op+Zuh4ODdh8ZCAeKPKlfIR1bZbcrztF+24IjYujurAiPzvvEWvQ8q 6OS80bW9L6br5g6/RzGum1cHTc97rzJlc85XZ7bgkmk/8+ffVWIpzkg01GIuKk4EAGdLZCG0 AgAA DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160412_040734_162567_04CF86F3 X-CRM114-Status: GOOD ( 10.70 ) X-Spam-Score: -7.9 (-------) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: k.kozlowski@samsung.com, linux-samsung-soc@vger.kernel.org, mturquette@baylibre.com, sboyd@codeaurora.org, linux-kernel@vger.kernel.org, tomasz.figa@gmail.com, thomas.ab@samsung.com, linux-clk@vger.kernel.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch enables clocks for CMU_CCORE and CMU_FSYS0 blocks. This is required before accessing registers of these blocks. Signed-off-by: Alim Akhtar --- drivers/clk/samsung/clk-exynos7.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c index ad68d46..7013aa7 100644 --- a/drivers/clk/samsung/clk-exynos7.c +++ b/drivers/clk/samsung/clk-exynos7.c @@ -8,6 +8,7 @@ * */ +#include #include #include @@ -205,7 +206,11 @@ static struct samsung_cmu_info topc_cmu_info __initdata = { static void __init exynos7_clk_topc_init(struct device_node *np) { + struct clk *clk; + samsung_cmu_register_one(np, &topc_cmu_info); + clk = __clk_lookup("aclk_ccore_133"); + clk_prepare_enable(clk); } CLK_OF_DECLARE(exynos7_clk_topc, "samsung,exynos7-clock-topc", @@ -573,7 +578,11 @@ static struct samsung_cmu_info top1_cmu_info __initdata = { static void __init exynos7_clk_top1_init(struct device_node *np) { + struct clk *clk; + samsung_cmu_register_one(np, &top1_cmu_info); + clk = __clk_lookup("aclk_fsys0_200"); + clk_prepare_enable(clk); } CLK_OF_DECLARE(exynos7_clk_top1, "samsung,exynos7-clock-top1",