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[79.184.217.18]) by smtp.gmail.com with ESMTPSA id r204sm24248948wmg.20.2016.04.15.12.55.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 15 Apr 2016 12:55:54 -0700 (PDT) From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= To: Boris Brezillon Subject: [PATCH 12/12] mtd: mtd: drop NAND_ECC_SOFT_BCH enum value Date: Fri, 15 Apr 2016 21:54:12 +0200 Message-Id: <1460750052-16285-13-git-send-email-zajec5@gmail.com> X-Mailer: git-send-email 1.8.4.5 In-Reply-To: <1460750052-16285-1-git-send-email-zajec5@gmail.com> References: <1460750052-16285-1-git-send-email-zajec5@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160415_125617_309057_75D5FE26 X-CRM114-Status: GOOD ( 15.73 ) X-Spam-Score: -2.5 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Weinberger , =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= , open list , Chen-Yu Tsai , linux-mtd@lists.infradead.org, Maxime Ripard , Brian Norris , David Woodhouse , "moderated list:ARM/Allwinner sunXi SoC support" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.1 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This value should not be part of nand_ecc_modes_t as it specifies algorithm not a mode. We successfully managed to introduce new "algo" field which is respected now. Signed-off-by: Rafa? Mi?ecki --- drivers/mtd/nand/fsmc_nand.c | 3 +-- drivers/mtd/nand/jz4780_nand.c | 1 - drivers/mtd/nand/nand_base.c | 2 -- drivers/mtd/nand/nandsim.c | 2 +- drivers/mtd/nand/sunxi_nand.c | 2 -- include/linux/mtd/nand.h | 1 - 6 files changed, 2 insertions(+), 9 deletions(-) diff --git a/drivers/mtd/nand/fsmc_nand.c b/drivers/mtd/nand/fsmc_nand.c index 0f8c63f..d4f454a 100644 --- a/drivers/mtd/nand/fsmc_nand.c +++ b/drivers/mtd/nand/fsmc_nand.c @@ -959,7 +959,6 @@ static int __init fsmc_nand_probe(struct platform_device *pdev) break; case NAND_ECC_SOFT: - case NAND_ECC_SOFT_BCH: if (nand->ecc.algo == NAND_ECC_BCH) { dev_info(&pdev->dev, "Using 4-bit SW BCH ECC scheme\n"); break; @@ -974,7 +973,7 @@ static int __init fsmc_nand_probe(struct platform_device *pdev) * Don't set layout for BCH4 SW ECC. This will be * generated later in nand_bch_init() later. */ - if (nand->ecc.mode != NAND_ECC_SOFT_BCH) { + if (nand->ecc.mode == NAND_ECC_HW) { switch (mtd->oobsize) { case 16: case 64: diff --git a/drivers/mtd/nand/jz4780_nand.c b/drivers/mtd/nand/jz4780_nand.c index 10f249a..daf3c42 100644 --- a/drivers/mtd/nand/jz4780_nand.c +++ b/drivers/mtd/nand/jz4780_nand.c @@ -179,7 +179,6 @@ static int jz4780_nand_init_ecc(struct jz4780_nand_chip *nand, struct device *de chip->ecc.correct = jz4780_nand_ecc_correct; /* fall through */ case NAND_ECC_SOFT: - case NAND_ECC_SOFT_BCH: dev_info(dev, "using %s (strength %d, size %d, bytes %d)\n", (nfc->bch) ? "hardware BCH" : "software ECC", chip->ecc.strength, chip->ecc.size, chip->ecc.bytes); diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index ffd1b32..186d5b5 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -4248,7 +4248,6 @@ int nand_scan_tail(struct mtd_info *mtd) ecc->algo = NAND_ECC_HAMMING; case NAND_ECC_SOFT: - case NAND_ECC_SOFT_BCH: switch (ecc->algo) { case NAND_ECC_HAMMING: ecc->calculate = nand_calculate_ecc; @@ -4386,7 +4385,6 @@ int nand_scan_tail(struct mtd_info *mtd) /* Large page NAND with SOFT_ECC should support subpage reads */ switch (ecc->mode) { case NAND_ECC_SOFT: - case NAND_ECC_SOFT_BCH: if (chip->page_shift > 9) chip->options |= NAND_SUBPAGE_READ; break; diff --git a/drivers/mtd/nand/nandsim.c b/drivers/mtd/nand/nandsim.c index 6ff1d8d..b0074c2 100644 --- a/drivers/mtd/nand/nandsim.c +++ b/drivers/mtd/nand/nandsim.c @@ -2339,7 +2339,7 @@ static int __init ns_init_module(void) retval = -EINVAL; goto error; } - chip->ecc.mode = NAND_ECC_SOFT_BCH; + chip->ecc.mode = NAND_ECC_SOFT; chip->ecc.algo = NAND_ECC_BCH; chip->ecc.size = 512; chip->ecc.strength = bch; diff --git a/drivers/mtd/nand/sunxi_nand.c b/drivers/mtd/nand/sunxi_nand.c index 1baf8983..a83a690 100644 --- a/drivers/mtd/nand/sunxi_nand.c +++ b/drivers/mtd/nand/sunxi_nand.c @@ -1612,8 +1612,6 @@ static int sunxi_nand_ecc_init(struct mtd_info *mtd, struct nand_ecc_ctrl *ecc, return -EINVAL; switch (ecc->mode) { - case NAND_ECC_SOFT_BCH: - break; case NAND_ECC_HW: ret = sunxi_nand_hw_ecc_ctrl_init(mtd, ecc, np); if (ret) diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h index e851839..fbe8e16 100644 --- a/include/linux/mtd/nand.h +++ b/include/linux/mtd/nand.h @@ -116,7 +116,6 @@ typedef enum { NAND_ECC_HW, NAND_ECC_HW_SYNDROME, NAND_ECC_HW_OOB_FIRST, - NAND_ECC_SOFT_BCH, } nand_ecc_modes_t; enum nand_ecc_algo {