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[80.11.198.90]) by smtp.gmail.com with ESMTPSA id x2sm1169329wjr.33.2016.04.19.09.56.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 19 Apr 2016 09:56:43 -0700 (PDT) From: Eric Auger To: eric.auger@st.com, eric.auger@linaro.org, robin.murphy@arm.com, alex.williamson@redhat.com, will.deacon@arm.com, joro@8bytes.org, tglx@linutronix.de, jason@lakedaemon.net, marc.zyngier@arm.com, christoffer.dall@linaro.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v7 01/10] iommu: Add DOMAIN_ATTR_MSI_MAPPING attribute Date: Tue, 19 Apr 2016 16:56:25 +0000 Message-Id: <1461084994-2355-2-git-send-email-eric.auger@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1461084994-2355-1-git-send-email-eric.auger@linaro.org> References: <1461084994-2355-1-git-send-email-eric.auger@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160419_095706_625219_B6970A63 X-CRM114-Status: GOOD ( 13.38 ) X-Spam-Score: -2.7 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: julien.grall@arm.com, patches@linaro.org, Jean-Philippe.Brucker@arm.com, p.fedin@samsung.com, linux-kernel@vger.kernel.org, Bharat.Bhushan@freescale.com, iommu@lists.linux-foundation.org, pranav.sawargaonkar@gmail.com MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Introduce a new DOMAIN_ATTR_MSI_MAPPING domain attribute. If supported, this means the MSI addresses need to be mapped in the IOMMU. x86 IOMMUs typically don't expose the attribute since on x86, MSI write transaction addresses always are within the 1MB PA region [FEE0_0000h - FEF0_000h] window which directly targets the APIC configuration space and hence bypass the sMMU. On ARM and PowerPC however MSI transactions are conveyed through the IOMMU. Signed-off-by: Bharat Bhushan Signed-off-by: Eric Auger --- v4 -> v5: - introduce the user in the next patch RFC v1 -> v1: - the data field is not used - for this attribute domain_get_attr simply returns 0 if the MSI_MAPPING capability if needed or <0 if not. - removed struct iommu_domain_msi_maps --- include/linux/iommu.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/linux/iommu.h b/include/linux/iommu.h index 62a5eae..b3e8c5b 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -113,6 +113,7 @@ enum iommu_attr { DOMAIN_ATTR_FSL_PAMU_ENABLE, DOMAIN_ATTR_FSL_PAMUV1, DOMAIN_ATTR_NESTING, /* two stages of translation */ + DOMAIN_ATTR_MSI_MAPPING, /* Require MSIs mapping in iommu */ DOMAIN_ATTR_MAX, };