From patchwork Thu Apr 21 08:18:16 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vladimir Murzin X-Patchwork-Id: 8897021 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id CAA0F9F457 for ; Thu, 21 Apr 2016 08:21:18 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id D923B202FE for ; Thu, 21 Apr 2016 08:21:17 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DF800200FF for ; Thu, 21 Apr 2016 08:21:16 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1at9pu-0007Yf-6g; Thu, 21 Apr 2016 08:19:42 +0000 Received: from foss.arm.com ([217.140.101.70]) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1at9pO-0007HL-28 for linux-arm-kernel@lists.infradead.org; Thu, 21 Apr 2016 08:19:11 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6AE44521; Thu, 21 Apr 2016 01:17:34 -0700 (PDT) Received: from login1.euhpc.arm.com (login1.euhpc.arm.com [10.6.26.143]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 4546D3F218; Thu, 21 Apr 2016 01:18:50 -0700 (PDT) From: Vladimir Murzin To: linux@arm.linux.org.uk Subject: [PATCH RFC 04/10] ARM: V7M: Add support for reading the CTR with CPUID_CACHETYPE Date: Thu, 21 Apr 2016 09:18:16 +0100 Message-Id: <1461226702-27160-5-git-send-email-vladimir.murzin@arm.com> X-Mailer: git-send-email 2.0.0 In-Reply-To: <1461226702-27160-1-git-send-email-vladimir.murzin@arm.com> References: <1461226702-27160-1-git-send-email-vladimir.murzin@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160421_011910_147942_D009A783 X-CRM114-Status: GOOD ( 14.32 ) X-Spam-Score: -7.9 (-------) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mcoquelin.stm32@gmail.com, manabian@gmail.com, stefan@agner.ch, kbuild-all@01.org, kernel@pengutronix.de, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Jonathan Austin With the addition of caches to the V7M Architecture a new Cache Type Register (CTR) is defined at 0xE000ED7C. This register serves the same purpose as the V7A/R version, called CPUID_CACHETYPE in the kernel. This patch adds appropriate definitions to the cpuid macros to allow the CTR to be read with read_cpuid(reg). Signed-off-by: Jonathan Austin Signed-off-by: Vladimir Murzin --- arch/arm/include/asm/cachetype.h | 15 +++++++++++++++ arch/arm/include/asm/cputype.h | 3 ++- arch/arm/kernel/setup.c | 9 +++++---- 3 files changed, 22 insertions(+), 5 deletions(-) diff --git a/arch/arm/include/asm/cachetype.h b/arch/arm/include/asm/cachetype.h index 8609de8..d55b7de 100644 --- a/arch/arm/include/asm/cachetype.h +++ b/arch/arm/include/asm/cachetype.h @@ -67,6 +67,7 @@ static inline unsigned int __attribute__((pure)) cacheid_is(unsigned int mask) #define CSSELR_L6 (5 << 1) #define CSSELR_L7 (6 << 1) +#ifndef CONFIG_CPU_V7M static inline void set_csselr(unsigned int cache_selector) { asm volatile("mcr p15, 2, %0, c0, c0, 0" : : "r" (cache_selector)); @@ -79,5 +80,19 @@ static inline unsigned int read_ccsidr(void) asm volatile("mrc p15, 1, %0, c0, c0, 0" : "=r" (val)); return val; } +#else /* CONFIG_CPU_V7M */ +#include +#include "asm/v7m.h" + +static inline void set_csselr(unsigned int cache_selector) +{ + writel(cache_selector, (void *)(BASEADDR_V7M_SCB + V7M_SCB_CTR)); +} + +static inline unsigned int read_ccsidr(void) +{ + return readl(BASEADDR_V7M_SCB + V7M_SCB_CCSIDR); +} +#endif #endif diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h index 2d46425..ea595db 100644 --- a/arch/arm/include/asm/cputype.h +++ b/arch/arm/include/asm/cputype.h @@ -7,7 +7,7 @@ #ifdef CONFIG_CPU_V7M #define CPUID_ID 0x0 -#define CPUID_CACHETYPE -1 +#define CPUID_CACHETYPE 0x7c #define CPUID_TCM -1 #define CPUID_TLBTYPE -1 #define CPUID_MPIDR -1 @@ -126,6 +126,7 @@ static inline unsigned int __attribute_const__ read_cpuid(unsigned offset) { switch (offset) { case CPUID_ID: + case CPUID_CACHETYPE: return readl(BASEADDR_V7M_SCB + offset); default: WARN_ON_ONCE(1); diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index 163a90d..596be88 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c @@ -313,11 +313,12 @@ static void __init cacheid_init(void) { unsigned int arch = cpu_architecture(); - if (arch == CPU_ARCH_ARMv7M) { - cacheid = 0; - } else if (arch >= CPU_ARCH_ARMv6) { + if (arch >= CPU_ARCH_ARMv6) { unsigned int cachetype = read_cpuid_cachetype(); - if ((cachetype & (7 << 29)) == 4 << 29) { + + if ((arch == CPU_ARCH_ARMv7M) && !cachetype) { + cacheid = 0; + } else if ((cachetype & (7 << 29)) == 4 << 29) { /* ARMv7 register format */ arch = CPU_ARCH_ARMv7; cacheid = CACHEID_VIPT_NONALIASING;