From patchwork Tue May 3 17:14:19 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Priit Laes X-Patchwork-Id: 9006381 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 0D971BF29F for ; Tue, 3 May 2016 17:16:51 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 4388D202C8 for ; Tue, 3 May 2016 17:16:50 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 09237202DD for ; Tue, 3 May 2016 17:16:49 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1axduW-0007FU-JK; Tue, 03 May 2016 17:15:00 +0000 Received: from plaes.org ([188.166.43.21]) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1axduU-0007Cb-3M for linux-arm-kernel@lists.infradead.org; Tue, 03 May 2016 17:14:58 +0000 Received: from localhost (63-220-191-90.dyn.estpak.ee [90.191.220.63]) by plaes.org (Postfix) with ESMTPSA id B4D97412C8; Tue, 3 May 2016 17:14:30 +0000 (UTC) From: Priit Laes To: Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Russell King , Maxime Ripard , Chen-Yu Tsai Subject: [PATCH 2/2] ARM: sun7i: dt: Add pll3 and pll7 clocks Date: Tue, 3 May 2016 20:14:19 +0300 Message-Id: <1462295659-6945-3-git-send-email-plaes@plaes.org> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1462295659-6945-1-git-send-email-plaes@plaes.org> References: <1462295659-6945-1-git-send-email-plaes@plaes.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160503_101458_317953_01211D2A X-CRM114-Status: UNSURE ( 8.66 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -2.9 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-sunxi@googlegroups.com, Priit Laes , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Enable pll3 and pll7 clocks that are needed by display clocks. --- arch/arm/boot/dts/sun7i-a20.dtsi | 41 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index bf5d056..2688512 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -187,6 +187,15 @@ clock-output-names = "osc24M"; }; + osc3M: osc3M_clk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <8>; + clock-mult = <1>; + clocks = <&osc24M>; + clock-output-names = "osc3M"; + }; + osc32k: clk@0 { #clock-cells = <0>; compatible = "fixed-clock"; @@ -211,6 +220,22 @@ "pll2-4x", "pll2-8x"; }; + pll3: clk@01c20010 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-pll3-clk"; + reg = <0x01c20010 0x4>; + clock = <&osc3M>; + clock-output-names = "pll3"; +}; + + pll3x2: pll3x2_clk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <1>; + clock-mult = <2>; + clock-output-names = "pll3-2x"; + }; + pll4: clk@01c20018 { #clock-cells = <0>; compatible = "allwinner,sun7i-a20-pll4-clk"; @@ -236,6 +261,22 @@ "pll6_div_4"; }; + pll7: clk@01c20030 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-pll3-clk"; + reg = <0x01c20030 0x4>; + clock = <&osc3M>; + clock-output-names = "pll7"; +}; + + pll7x2: pll7x2_clk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <1>; + clock-mult = <2>; + clock-output-names = "pll7-2x"; + }; + pll8: clk@01c20040 { #clock-cells = <0>; compatible = "allwinner,sun7i-a20-pll4-clk";