From patchwork Tue May 3 23:47:25 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ray Jui X-Patchwork-Id: 9008851 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 0748D9F1C1 for ; Tue, 3 May 2016 23:49:53 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 0998D2034B for ; Tue, 3 May 2016 23:49:52 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 12EB520328 for ; Tue, 3 May 2016 23:49:51 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1axk3W-0005Wc-PC; Tue, 03 May 2016 23:48:42 +0000 Received: from mail-gw3-out.broadcom.com ([216.31.210.64]) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1axk3S-0005L8-Dm for linux-arm-kernel@lists.infradead.org; Tue, 03 May 2016 23:48:39 +0000 X-IronPort-AV: E=Sophos;i="5.24,574,1455004800"; d="scan'208";a="94137904" Received: from mail-irv-18.broadcom.com ([10.15.198.37]) by mail-gw3-out.broadcom.com with ESMTP; 03 May 2016 17:01:59 -0700 Received: from mail-irva-12.broadcom.com (mail-irva-12.broadcom.com [10.11.16.101]) by mail-irv-18.broadcom.com (Postfix) with ESMTP id 93BA582023; Tue, 3 May 2016 16:48:08 -0700 (PDT) Received: from smtphost.broadcom.com (lbrmn-lnxub44.ric.broadcom.com [10.136.8.49]) by mail-irva-12.broadcom.com (Postfix) with ESMTP id A7BF11277DD; Tue, 3 May 2016 16:47:29 -0700 (PDT) From: Ray Jui To: Thomas Gleixner , Jason Cooper , Marc Zyngier Subject: [PATCH 2/2] irqchip/gic-v2m: Add workaround for Broadcom NS2 GICv2m erratum Date: Tue, 3 May 2016 16:47:25 -0700 Message-Id: <1462319245-32532-3-git-send-email-ray.jui@broadcom.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1462319245-32532-1-git-send-email-ray.jui@broadcom.com> References: <1462319245-32532-1-git-send-email-ray.jui@broadcom.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160503_164838_769103_19ABBD94 X-CRM114-Status: GOOD ( 15.48 ) X-Spam-Score: -5.2 (-----) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ray Jui , bcm-kernel-feedback-list@broadcom.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Alex Barba MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Alex Barba discovered Broadcom NS2 GICv2m implementation has an erratum where the MSI data needs to be the SPI number subtracted by an offset of 32, for the correct MSI interrupt to be triggered. We are aware that APM X-Gene GICv2m has a similar erratum where the MSI data needs to be the offset from the spi_start. While APM's workaround is triggered based on readings from the MSI_IIDR register, this patch contains a more general solution by allowing this offset to be specified with an optional DT property 'arm,msi-offset-spi'. This patch also maintains compatibility with existing APM platforms Reported-by: Alex Barba Signed-off-by: Ray Jui Reviewed-by: Alex Barba --- drivers/irqchip/irq-gic-v2m.c | 35 +++++++++++++++++++++++++++++------ 1 file changed, 29 insertions(+), 6 deletions(-) diff --git a/drivers/irqchip/irq-gic-v2m.c b/drivers/irqchip/irq-gic-v2m.c index 28f047c..7f58b87 100644 --- a/drivers/irqchip/irq-gic-v2m.c +++ b/drivers/irqchip/irq-gic-v2m.c @@ -62,6 +62,7 @@ struct v2m_data { void __iomem *base; /* GICv2m virt address */ u32 spi_start; /* The SPI number that MSIs start */ u32 nr_spis; /* The number of SPIs for MSIs */ + u32 spi_offset; /* offset to be subtracted from SPI number */ unsigned long *bm; /* MSI vector bitmap */ u32 flags; /* v2m flags for specific implementation */ }; @@ -102,7 +103,7 @@ static void gicv2m_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) msg->data = data->hwirq; if (v2m->flags & GICV2M_NEEDS_SPI_OFFSET) - msg->data -= v2m->spi_start; + msg->data -= v2m->spi_offset; } static struct irq_chip gicv2m_irq_chip = { @@ -294,7 +295,7 @@ static int gicv2m_allocate_domains(struct irq_domain *parent) } static int __init gicv2m_init_one(struct fwnode_handle *fwnode, - u32 spi_start, u32 nr_spis, + u32 spi_start, u32 nr_spis, u32 spi_offset, struct resource *res) { int ret; @@ -341,8 +342,24 @@ static int __init gicv2m_init_one(struct fwnode_handle *fwnode, * the MSI data is the absolute value within the range from * spi_start to (spi_start + num_spis). */ - if (readl_relaxed(v2m->base + V2M_MSI_IIDR) == XGENE_GICV2M_MSI_IIDR) + if (readl_relaxed(v2m->base + V2M_MSI_IIDR) == XGENE_GICV2M_MSI_IIDR) { v2m->flags |= GICV2M_NEEDS_SPI_OFFSET; + v2m->spi_offset = v2m->spi_start; + } + + /* + * Various GICv2m implementations may require the MSI data to be the SPI + * number subtracted by an offset, in order to trigger the correct MSI + * interrupt. This offset can be different depending on how gicv2m is + * integrated into an SoC. + * + * 'spi_offset' becomes non-zero here if optional DT property + * 'arm,msi-offset-spi' is specified (with an non-zero offset) + */ + if (spi_offset) { + v2m->flags |= GICV2M_NEEDS_SPI_OFFSET; + v2m->spi_offset = spi_offset; + } v2m->bm = kzalloc(sizeof(long) * BITS_TO_LONGS(v2m->nr_spis), GFP_KERNEL); @@ -378,7 +395,7 @@ static int __init gicv2m_of_init(struct fwnode_handle *parent_handle, for (child = of_find_matching_node(node, gicv2m_device_id); child; child = of_find_matching_node(child, gicv2m_device_id)) { - u32 spi_start = 0, nr_spis = 0; + u32 spi_start = 0, nr_spis = 0, spi_offset = 0; struct resource res; if (!of_find_property(child, "msi-controller", NULL)) @@ -396,7 +413,13 @@ static int __init gicv2m_of_init(struct fwnode_handle *parent_handle, pr_info("DT overriding V2M MSI_TYPER (base:%u, num:%u)\n", spi_start, nr_spis); - ret = gicv2m_init_one(&child->fwnode, spi_start, nr_spis, &res); + if (!of_property_read_u32(child, "arm,msi-offset-spi", + &spi_offset)) + pr_info("DT configuring V2M spi offset:%u\n", + spi_offset); + + ret = gicv2m_init_one(&child->fwnode, spi_start, nr_spis, + spi_offset, &res); if (ret) { of_node_put(child); break; @@ -460,7 +483,7 @@ acpi_parse_madt_msi(struct acpi_subtable_header *header, return -EINVAL; } - ret = gicv2m_init_one(fwnode, spi_start, nr_spis, &res); + ret = gicv2m_init_one(fwnode, spi_start, nr_spis, 0, &res); if (ret) irq_domain_free_fwnode(fwnode);