From patchwork Mon May 9 12:31:50 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Stanley X-Patchwork-Id: 9046081 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id AB7BCBF440 for ; Mon, 9 May 2016 12:34:52 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id A4D9F2012D for ; Mon, 9 May 2016 12:34:51 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 961BC2010E for ; Mon, 9 May 2016 12:34:50 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1azkN2-0003gf-Iw; Mon, 09 May 2016 12:33:08 +0000 Received: from mail-pa0-x22c.google.com ([2607:f8b0:400e:c03::22c]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1azkMe-0002qV-Tb for linux-arm-kernel@lists.infradead.org; Mon, 09 May 2016 12:32:46 +0000 Received: by mail-pa0-x22c.google.com with SMTP id xk12so72839904pac.0 for ; Mon, 09 May 2016 05:32:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=jms.id.au; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=6u99OSoHM6ehffeKnUQK5Wtg46Qc60D4ebj+2zOlsho=; b=CjuBvmssQD/FjZ4Guk0FJa3xlpJLbkS1hR/07lMSEMUii2jALI8Yb2XXHCI4qBeMsh gaYpWAezZJmv0NtoruVjjj2LjHXDFdYhvyQc4a4zFMB24xU6NcbnhVh9iQjM3H+67Ev2 juzeTaHDBHch27ivTN4VEN/1tdYfYL8BhX13M= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=6u99OSoHM6ehffeKnUQK5Wtg46Qc60D4ebj+2zOlsho=; b=JUJH3GikhPfFRrcoWmJEx17/q7FjiMaKq1Bm09YVuBL6R/CW6HXkXykzGR6P69nNL2 YiA4IeHvZ5h2HxCCnHNEaBXeRd+hbd8XPyQ8Hhg1dmMA5cpOrTdea28+1XklAGFDMUif pYbhMpaUxKnysZqeD8KdAuvD/gooNZ0RtNqhvonQP1JhzALlSjRtKaEm2mYzNDOj3PVo TN8m1seJwRwPN3CDHB+9iJuUmelyVzydcBmQtqaDCVj9raq4/jyKKhttaigqa7JstVxd gPqg7R2tJvOSztRXBF37HYVFv7aVHbxa0Gr7UZ/91D7upFrdc4Dw5E1P5/ZW8zzsjJ/J RO7Q== X-Gm-Message-State: AOPr4FXXngJ50p7WzmckpWpVgNeHiKs86abV7YiG5Rh3kkAqa5u7rH+lBQerHQnK4HhqUg== X-Received: by 10.67.22.129 with SMTP id hs1mr50178323pad.105.1462797143388; Mon, 09 May 2016 05:32:23 -0700 (PDT) Received: from icarus.au.ibm.com ([2403:480:11:10:3400:b218:cbe9:48cb]) by smtp.gmail.com with ESMTPSA id i75sm17021382pfj.51.2016.05.09.05.32.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 09 May 2016 05:32:22 -0700 (PDT) From: Joel Stanley To: mturquette@baylibre.com, sboyd@codeaurora.org Subject: [PATCH 3/4] drvers/clk: Support fifth generation Aspeed SoCs Date: Mon, 9 May 2016 22:01:50 +0930 Message-Id: <1462797111-14271-4-git-send-email-joel@jms.id.au> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1462797111-14271-1-git-send-email-joel@jms.id.au> References: <1462797111-14271-1-git-send-email-joel@jms.id.au> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160509_053245_095847_C1643411 X-CRM114-Status: GOOD ( 20.19 ) X-Spam-Score: -2.7 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, heiko@sntech.de, arnd@arndb.de, benh@kernel.crashing.org, jk@ozlabs.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-6.2 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP A basic driver to create fixed rate clock devices from strapping registers. Like the ast2400, the ast2500 clocks are derived from an external oscillator and the frequency of this can be determined from the strapping of the processor. The frequency of internal clocks can be derived from other registers in the SCU (System Control Unit). The layout of the internal clocks is a bit different to the ast2400, as are the divisor reigisters, so it has it's own driver. Signed-off-by: Joel Stanley --- drivers/clk/aspeed/Makefile | 1 + drivers/clk/aspeed/clk-g5.c | 189 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 190 insertions(+) create mode 100644 drivers/clk/aspeed/clk-g5.c diff --git a/drivers/clk/aspeed/Makefile b/drivers/clk/aspeed/Makefile index d3457fbe3019..9ddb0f8f4356 100644 --- a/drivers/clk/aspeed/Makefile +++ b/drivers/clk/aspeed/Makefile @@ -1 +1,2 @@ obj-$(CONFIG_MACH_ASPEED_G4) += clk-g4.o +obj-$(CONFIG_MACH_ASPEED_G5) += clk-g5.o diff --git a/drivers/clk/aspeed/clk-g5.c b/drivers/clk/aspeed/clk-g5.c new file mode 100644 index 000000000000..812fd9accf30 --- /dev/null +++ b/drivers/clk/aspeed/clk-g5.c @@ -0,0 +1,189 @@ +/* + * Copyright 2016 IBM Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +#include +#include +#include +#include +#include + +static void __init aspeed_of_clkin_clk_init(struct device_node *node) +{ + struct clk *clk; + void __iomem *base; + int reg, rate; + const char *name = node->name; + + of_property_read_string(node, "clock-output-names", &name); + + base = of_iomap(node, 0); + if (!base) { + pr_err("%s: of_iomap failed\n", node->full_name); + return; + } + /* Strap register SCU70 */ + reg = readl(base) & BIT(23); + iounmap(base); + + if (reg) + rate = 25 * 1000 * 1000; + else + rate = 24 * 1000 * 1000; + + clk = clk_register_fixed_rate(NULL, name, NULL, 0, rate); + if (IS_ERR(clk)) { + pr_err("%s: failed to register clock\n", node->full_name); + return; + } + + clk_register_clkdev(clk, NULL, name); + of_clk_add_provider(node, of_clk_src_simple_get, clk); +} +CLK_OF_DECLARE(aspeed_clkin_clock, "aspeed,g5-clkin-clock", + aspeed_of_clkin_clk_init); + + +static void __init aspeed_of_hpll_clk_init(struct device_node *node) +{ + struct clk *clk, *clkin_clk; + void __iomem *base; + int reg, rate, clkin; + const char *name = node->name; + const char *parent_name; + + of_property_read_string(node, "clock-output-names", &name); + parent_name = of_clk_get_parent_name(node, 0); + + base = of_iomap(node, 0); + if (!base) { + pr_err("%s: of_iomap failed\n", node->full_name); + return; + } + /* H-PLL parameter register SCU24 */ + reg = readl(base); + iounmap(base); + + clkin_clk = of_clk_get(node, 0); + if (IS_ERR(clkin_clk)) { + pr_err("%s: of_clk_get failed\n", node->full_name); + return; + } + + clkin = clk_get_rate(clkin_clk); + + if (reg & BIT(21)) { + rate = 0; + } else if (reg & BIT(20)) { + rate = clkin; + } else { + int p = (reg >> 13) & 0x3f; + int m = (reg >> 5) & 0xff; + int n = reg & 0x1f; + + rate = clkin * ((m + 1) / (n + 1)) / (p + 1); + } + + clk = clk_register_fixed_rate(NULL, name, parent_name, 0, rate); + if (IS_ERR(clk)) { + pr_err("%s: failed to register clock\n", node->full_name); + return; + } + + clk_register_clkdev(clk, NULL, name); + of_clk_add_provider(node, of_clk_src_simple_get, clk); +} +CLK_OF_DECLARE(aspeed_hpll_clock, "aspeed,g5-hpll-clock", + aspeed_of_hpll_clk_init); + + +static void __init aspeed_of_ahb_clk_init(struct device_node *node) +{ + struct clk *clk, *hpll_clk; + void __iomem *base; + int reg, rate, hpll; + const char *name = node->name; + const char *parent_name; + + of_property_read_string(node, "clock-output-names", &name); + parent_name = of_clk_get_parent_name(node, 0); + + /* Strap register SCU70 */ + base = of_iomap(node, 0); + if (!base) { + pr_err("%s: of_iomap failed\n", node->full_name); + return; + } + reg = (readl(base) >> 9) & 0x03; + iounmap(base); + + /* A value of zero is undefined */ + WARN_ON(reg == 0); + + hpll_clk = of_clk_get(node, 0); + if (IS_ERR(hpll_clk)) { + pr_err("%s: of_clk_get failed\n", node->full_name); + return; + } + + hpll = clk_get_rate(hpll_clk); + + rate = hpll / 2 / (reg + 1); + + clk = clk_register_fixed_rate(NULL, name, parent_name, 0, rate); + if (IS_ERR(clk)) { + pr_err("%s: failed to register clock\n", node->full_name); + return; + } + + clk_register_clkdev(clk, NULL, name); + of_clk_add_provider(node, of_clk_src_simple_get, clk); +} +CLK_OF_DECLARE(aspeed_ahb_clock, "aspeed,g5-ahb-clock", + aspeed_of_ahb_clk_init); + + +static void __init aspeed_of_apb_clk_init(struct device_node *node) +{ + struct clk *clk, *hpll_clk; + void __iomem *base; + int reg, rate; + const char *name = node->name; + const char *parent_name; + + of_property_read_string(node, "clock-output-names", &name); + parent_name = of_clk_get_parent_name(node, 0); + + /* Clock selection register SCU08 */ + base = of_iomap(node, 0); + if (!base) { + pr_err("%s: of_iomap failed\n", node->full_name); + return; + } + reg = readl(base) >> 23 & 0x3; + iounmap(base); + + hpll_clk = of_clk_get(node, 0); + if (IS_ERR(hpll_clk)) { + pr_err("%s: of_clk_get failed\n", node->full_name); + return; + } + + rate = clk_get_rate(hpll_clk) / (4 * (reg + 1)); + + clk = clk_register_fixed_rate(NULL, name, parent_name, 0, rate); + if (IS_ERR(clk)) { + pr_err("%s: failed to register clock\n", node->full_name); + return; + } + + clk_register_clkdev(clk, NULL, name); + of_clk_add_provider(node, of_clk_src_simple_get, clk); +} +CLK_OF_DECLARE(aspeed_apb_clock, "aspeed,g5-apb-clock", + aspeed_of_apb_clk_init);