From patchwork Tue May 10 20:09:07 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 9062221 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 5A6C4BF29F for ; Tue, 10 May 2016 20:15:23 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 6E43A200E5 for ; Tue, 10 May 2016 20:15:22 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7D14B200CC for ; Tue, 10 May 2016 20:15:21 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1b0E2K-00033b-VV; Tue, 10 May 2016 20:13:45 +0000 Received: from mail.kernel.org ([198.145.29.136]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1b0Dz8-0007MM-U4 for linux-arm-kernel@lists.infradead.org; Tue, 10 May 2016 20:10:36 +0000 Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 3CBC1201BC; Tue, 10 May 2016 20:10:07 +0000 (UTC) Received: from localhost.localdomain (89-66-181-234.dynamic.chello.pl [89.66.181.234]) (using TLSv1.2 with cipher AES128-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 6809B201C0; Tue, 10 May 2016 20:10:03 +0000 (UTC) From: Krzysztof Kozlowski To: Kukjin Kim , Krzysztof Kozlowski , Sylwester Nawrocki , Tomasz Figa , Michael Turquette , Stephen Boyd , linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v3 04/27] clk: samsung: exynos5410: Provide fin_pll external fixed clock Date: Tue, 10 May 2016 22:09:07 +0200 Message-Id: <1462910970-1812-5-git-send-email-krzk@kernel.org> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1462910970-1812-1-git-send-email-krzk@kernel.org> References: <1462910970-1812-1-git-send-email-krzk@kernel.org> X-Spam-Status: No, score=-6.3 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160510_131027_420882_D18123A3 X-CRM114-Status: GOOD ( 16.71 ) X-Spam-Score: -6.3 (------) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Javier Martinez Canillas , Rob Herring , Krzysztof Kozlowski MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Just like clock driver for Exynos542x/5800, provide the fixed clock here so the clock bindings and their consumers would be consistent and similar. However a clock named "fin_pll" is already provided by generic fixed-clock and it is both referenced in the clock driver (by name) and in DT (by phandle). To make the transition smooth, first introduce the new external fixed clock here under temporary, different name and switch internal users to it. Signed-off-by: Krzysztof Kozlowski Acked-by: Stephen Boyd Reviewed-by: Javier Martinez Canillas --- drivers/clk/samsung/clk-exynos5410.c | 42 +++++++++++++++++++++++++----------- 1 file changed, 29 insertions(+), 13 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5410.c b/drivers/clk/samsung/clk-exynos5410.c index d5d5dcabc4a9..35f2cb36f7ef 100644 --- a/drivers/clk/samsung/clk-exynos5410.c +++ b/drivers/clk/samsung/clk-exynos5410.c @@ -59,23 +59,29 @@ enum exynos5410_plls { }; /* list of all parent clocks */ -PNAME(apll_p) = { "fin_pll", "fout_apll", }; -PNAME(bpll_p) = { "fin_pll", "fout_bpll", }; -PNAME(cpll_p) = { "fin_pll", "fout_cpll" }; -PNAME(mpll_p) = { "fin_pll", "fout_mpll", }; -PNAME(kpll_p) = { "fin_pll", "fout_kpll", }; +PNAME(apll_p) = { "fin_pll_new", "fout_apll", }; +PNAME(bpll_p) = { "fin_pll_new", "fout_bpll", }; +PNAME(cpll_p) = { "fin_pll_new", "fout_cpll" }; +PNAME(mpll_p) = { "fin_pll_new", "fout_mpll", }; +PNAME(kpll_p) = { "fin_pll_new", "fout_kpll", }; PNAME(mout_cpu_p) = { "mout_apll", "sclk_mpll", }; PNAME(mout_kfc_p) = { "mout_kpll", "sclk_mpll", }; -PNAME(mpll_user_p) = { "fin_pll", "sclk_mpll", }; -PNAME(bpll_user_p) = { "fin_pll", "sclk_bpll", }; +PNAME(mpll_user_p) = { "fin_pll_new", "sclk_mpll", }; +PNAME(bpll_user_p) = { "fin_pll_new", "sclk_bpll", }; PNAME(mpll_bpll_p) = { "sclk_mpll_muxed", "sclk_bpll_muxed", }; -PNAME(group2_p) = { "fin_pll", "fin_pll", "none", "none", +PNAME(group2_p) = { "fin_pll_new", "fin_pll_new", "none", "none", "none", "none", "sclk_mpll_bpll", "none", "none", "sclk_cpll" }; +/* fixed rate clocks generated outside the soc */ +static struct samsung_fixed_rate_clock + exynos5x_fixed_rate_ext_clks[] __initdata = { + FRATE(CLK_FIN_PLL, "fin_pll_new", NULL, 0, 0), +}; + static struct samsung_mux_clock exynos5410_mux_clks[] __initdata = { MUX(0, "mout_apll", apll_p, SRC_CPU, 0, 1), MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1), @@ -168,18 +174,24 @@ static struct samsung_gate_clock exynos5410_gate_clks[] __initdata = { }; static struct samsung_pll_clock exynos5410_plls[nr_plls] __initdata = { - [apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK, + [apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll_new", APLL_LOCK, APLL_CON0, NULL), - [cpll] = PLL(pll_35xx, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK, + [cpll] = PLL(pll_35xx, CLK_FOUT_CPLL, "fout_cpll", "fin_pll_new", CPLL_LOCK, CPLL_CON0, NULL), - [mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK, + [mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll_new", MPLL_LOCK, MPLL_CON0, NULL), - [bpll] = PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK, + [bpll] = PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll_new", BPLL_LOCK, BPLL_CON0, NULL), - [kpll] = PLL(pll_35xx, CLK_FOUT_KPLL, "fout_kpll", "fin_pll", KPLL_LOCK, + [kpll] = PLL(pll_35xx, CLK_FOUT_KPLL, "fout_kpll", "fin_pll_new", KPLL_LOCK, KPLL_CON0, NULL), }; +/* Same as in Exynos5420 */ +static const struct of_device_id ext_clk_match[] __initconst = { + { .compatible = "samsung,exynos5420-oscclk", .data = (void *)0, }, + { }, +}; + /* register exynos5410 clocks */ static void __init exynos5410_clk_init(struct device_node *np) { @@ -192,6 +204,10 @@ static void __init exynos5410_clk_init(struct device_node *np) ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS); + samsung_clk_of_register_fixed_ext(ctx, exynos5x_fixed_rate_ext_clks, + ARRAY_SIZE(exynos5x_fixed_rate_ext_clks), + ext_clk_match); + samsung_clk_register_pll(ctx, exynos5410_plls, ARRAY_SIZE(exynos5410_plls), reg_base);