From patchwork Fri May 13 14:00:11 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 9091751 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id CF2989F1C1 for ; Fri, 13 May 2016 14:02:43 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id B6BFC20260 for ; Fri, 13 May 2016 14:02:42 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8840F2026D for ; Fri, 13 May 2016 14:02:41 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1b1DeX-00068v-2W; Fri, 13 May 2016 14:01:17 +0000 Received: from mail-wm0-x22b.google.com ([2a00:1450:400c:c09::22b]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1b1DeA-0005il-GY for linux-arm-kernel@lists.infradead.org; Fri, 13 May 2016 14:00:56 +0000 Received: by mail-wm0-x22b.google.com with SMTP id e201so23924355wme.0 for ; Fri, 13 May 2016 07:00:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=7fWN+0b8quWVDg38p8P+UENr7FpbFqbrJyn+96qoKaI=; b=BbLqM9tWdS88LiHOxzi21ciKsHQW8/MROQudyouCjan3w/z8k4GPSTV9o+ySyl3Mkd 6C/Xfz8xVRFwsOCXU+K1PW7amaAsbrOvqCoDK9fPHaiW1R5Th+1FUNuL51Slx2LlpvPl yDRbij2/nbuO6MgQFASz94CKd9wzie+2jW6V2QJdkZ7ah+FESuKFORkqRG2aySKKqS2j jDu1XnyyWEhvPzjRUodVWaJpqdnJJuwYoQrht6SgQPWx9iGB+wc3lIbPpGolluV0JNN1 661QW2g16MolQDtUHfUO+hx3tvGylmrZACjqZhb+gLxHutmtp+Ef6F2nXl8AEMqF3KMO AhOw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=7fWN+0b8quWVDg38p8P+UENr7FpbFqbrJyn+96qoKaI=; b=Ri63sQpdx5EKcUmoD5J7iuAYrRz9FATYBbpDZCjuFTl5E7KGvrhpXMnKnVaU+egtet tAKgv2EerxxaQ4hGApL8/ZMaUJPU1Shzbgamp7CnG0ooNmUePvWxAjgWZAKDQ+NHMQp5 K3q8CGohrB3VxXeDZFcM+WkBMMB4NAtpgf9QJB9oGwosa/BK7qImnQN/gzgbCven0umb K2uWprR6GY12arvzmeC9cz8+BKJ6W46S2vjcIkcvZIYE522/ty8ANGd7c4t4Pxt7sepy d2J8ZgRnRCGaCDvPyedQp+A0Gnxojk8u5vhUXX/LQeE0LHjGTzMVNmcFkrj+LZAgTOcu UCzg== X-Gm-Message-State: AOPr4FUILgJuArepUGkhBXNqXUWVMxRY1gd1Cqsv/1rvsvNdUsTD9M7bLydzGPe+ZPwR++Ln X-Received: by 10.194.223.41 with SMTP id qr9mr15886342wjc.61.1463148032436; Fri, 13 May 2016 07:00:32 -0700 (PDT) Received: from localhost.localdomain ([90.63.244.31]) by smtp.gmail.com with ESMTPSA id d1sm18749091wjb.47.2016.05.13.07.00.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 13 May 2016 07:00:31 -0700 (PDT) From: Neil Armstrong To: linux-kernel@vger.kernel.org, p.zabel@pengutronix.de, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org Subject: [RFC PATCH 2/3] dt-bindings: reset: Add bindings for the Meson GXBB Reset Controller Date: Fri, 13 May 2016 16:00:11 +0200 Message-Id: <1463148012-25988-3-git-send-email-narmstrong@baylibre.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1463148012-25988-1-git-send-email-narmstrong@baylibre.com> References: <1463148012-25988-1-git-send-email-narmstrong@baylibre.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160513_070054_980285_F9EC0BF3 X-CRM114-Status: GOOD ( 17.73 ) X-Spam-Score: -1.9 (-) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Neil Armstrong MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.5 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add DT bindings for the Meson GXBB SoC Reset Controller documentation and the associated include file. Signed-off-by: Neil Armstrong --- .../bindings/reset/amlogic,meson-gxbb-reset.txt | 16 +++ .../dt-bindings/reset/amlogic,meson-gxbb-reset.h | 160 +++++++++++++++++++++ 2 files changed, 176 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/amlogic,meson-gxbb-reset.txt create mode 100644 include/dt-bindings/reset/amlogic,meson-gxbb-reset.h diff --git a/Documentation/devicetree/bindings/reset/amlogic,meson-gxbb-reset.txt b/Documentation/devicetree/bindings/reset/amlogic,meson-gxbb-reset.txt new file mode 100644 index 0000000..8761317 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/amlogic,meson-gxbb-reset.txt @@ -0,0 +1,16 @@ +Amlogic Meson GXBB SoC Reset Controller +======================================= + +Please also refer to reset.txt in this directory for common reset +controller binding usage. + +Required properties: +- compatible: Should be "amlogic,meson-gxbb-reset" +- #reset-cells: 1, see below + +example: + +reset: reset-controller { + compatible = "amlogic,meson-gxbb-reset"; + #reset-cells = <1>; +}; diff --git a/include/dt-bindings/reset/amlogic,meson-gxbb-reset.h b/include/dt-bindings/reset/amlogic,meson-gxbb-reset.h new file mode 100644 index 0000000..44e73b8 --- /dev/null +++ b/include/dt-bindings/reset/amlogic,meson-gxbb-reset.h @@ -0,0 +1,160 @@ +/* + * Copyright (c) 2016 BayLibre, Inc. + * Author: Neil Armstrong + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _DT_BINDINGS_AMLOGIC_MESON_GXBB_RESET_H +#define _DT_BINDINGS_AMLOGIC_MESON_GXBB_RESET_H + +#define RESET_VCBUS 0 +/* 1 */ +/* 2 */ +#define RESET_GIC 3 +#define RESET_CAPB3_DECODE 4 +#define RESET_NAND_CAPB3 5 +#define RESET_HDMITX_CAPB3 6 +#define RESET_MALI_CAPB3 7 +#define RESET_DOS_CAPB3 8 +#define RESET_SYS_CPU_CAPB3 9 +#define RESET_CBUS_CAPB3 10 +#define RESET_AHB_CNTL 11 +#define RESET_AHB_DATA 12 +#define RESET_VCBUS_CLK81 13 +#define RESET_MMC 14 +#define RESET_MIPI 15 +#define RESET_PARSER 16 +#define RESET_BLKMV 17 +#define RESET_ISA 18 +#define RESET_Ethernet 19 +#define RESET_SD_EMMC_A 20 +#define RESET_SD_EMMC_B 21 +#define RESET_SD_EMMC_C 22 +#define RESET_ROM_BOOT 23 +#define RESET_SYS_CPU_3_0 24 +#define RESET_SYS_CPU_CORE_3_0 25 +#define RESET_SYS_PLL_DIV 26 +#define RESET_SYS_CPU_AXI 27 +#define RESET_SYS_CPU_L2 28 +#define RESET_SYS_CPU_P 29 +#define RESET_SYS_CPU_MBIST 30 +/* 31 */ +#define RESET_VD_RMEM 32 +#define RESET_AUDIN 33 +#define RESET_HDMI_TX 34 +/* 35 */ +/* 36 */ +/* 37 */ +#define RESET_GE2D 38 +#define RESET_PARSER_REG 39 +#define RESET_PARSER_FETCH 40 +#define RESET_PARSER_CTL 41 +#define RESET_PARSER_TOP 42 +/* 43 */ +/* 44 */ +#define RESET_AO_CPU_RESET 45 +#define RESET_MALI 46 +#define RESET_HDMI_SYSTEM_RESET 47 +#define RESET_RING_OSCILLATOR 48 +#define RESET_SYS_CPU 49 +#define RESET_EFUSE 50 +#define RESET_SYS_CPU_BVCI 51 +#define RESET_AIFIFO 52 +#define RESET_TVFE 53 +#define RESET_AHB_BRIDGE_CNTL 54 +/* 55 */ +#define RESET_AUDIO_DAC 56 +#define RESET_DEMUX_TOP 57 +#define RESET_DEMUX_DES 58 +#define RESET_DEMUX_S2P_0 59 +#define RESET_DEMUX_S2P_1 60 +#define RESET_DEMUX_RESET_0 61 +#define RESET_DEMUX_RESET_1 62 +#define RESET_DEMUX_RESET_2 63 +#define RESET_DDR_PLL 64 +#define RESET_MISC_PLL 65 +/* 66 */ +/* 67 */ +#define RESET_DVIN_RESET 68 +#define RESET_RDMA 69 +#define RESET_VENCI 70 +#define RESET_VENCP 71 +/* 72 */ +#define RESET_VDAC 73 +#define RESET_RTC 74 +/* 75 */ +#define RESET_VDI6 76 +#define RESET_VENCL 77 +#define RESET_I2C_MASTER_2 78 +#define RESET_I2C_MASTER_1 79 +#define RESET_PERIPHS_GENERAL 80 +#define RESET_PERIPHS_SPICC 81 +#define RESET_PERIPHS_SMART_CARD 82 +#define RESET_PERIPHS_SAR_ADC 83 +#define RESET_PERIPHS_I2C_MASTER_0 84 +#define RESET_SANA 85 +/* 86 */ +#define RESET_PERIPHS_STREAM_INTERFACE 87 +#define RESET_PERIPHS_SDIO 88 +#define RESET_PERIPHS_UART_0 89 +#define RESET_PERIPHS_UART_1_2 90 +#define RESET_PERIPHS_ASYNC_0 91 +#define RESET_PERIPHS_ASYNC_1 92 +#define RESET_PERIPHS_SPI_0 93 +#define RESET_PERIPHS_SDHC 94 +#define RESET_UART_SLIP 95 +#define RESET_USB_DDR_0 96 +#define RESET_USB_DDR_1 97 +#define RESET_USB_DDR_2 98 +#define RESET_USB_DDR_3 99 +/* 100 */ +#define RESET_DEVICE_MMC_ARB 101 +/* 102 */ +#define RESET_VID_LOCK 103 +#define RESET_A9_DMC_PIPEL 104 +/* 105 */ +/* 106 */ +/* 107 */ +/* 108 */ +/* 109 */ +/* 110 */ +/* 111 */ + +#endif