From patchwork Tue May 24 17:41:02 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Javier Martinez Canillas X-Patchwork-Id: 9133981 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 6196E607D7 for ; Tue, 24 May 2016 17:43:25 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5A057281FE for ; Tue, 24 May 2016 17:43:25 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4ED6F28258; Tue, 24 May 2016 17:43:25 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id D8CA1281FE for ; Tue, 24 May 2016 17:43:24 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1b5GLD-0008Nq-Cn; Tue, 24 May 2016 17:42:03 +0000 Received: from lists.s-osg.org ([54.187.51.154]) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1b5GL6-0008HD-Tx for linux-arm-kernel@lists.infradead.org; Tue, 24 May 2016 17:41:58 +0000 Received: from minerva.sisa.samsung.com (host-224.58.217.201.copaco.com.py [201.217.58.224]) by lists.s-osg.org (Postfix) with ESMTPSA id D3EC8E27AC; Tue, 24 May 2016 10:42:03 -0700 (PDT) From: Javier Martinez Canillas To: linux-kernel@vger.kernel.org Subject: [PATCH 2/2] ARM: dts: Add async-bridge clock to MFC power domain for Exynos5420 Date: Tue, 24 May 2016 13:41:02 -0400 Message-Id: <1464111662-15336-3-git-send-email-javier@osg.samsung.com> X-Mailer: git-send-email 2.5.5 In-Reply-To: <1464111662-15336-1-git-send-email-javier@osg.samsung.com> References: <1464111662-15336-1-git-send-email-javier@osg.samsung.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160524_104157_134455_CA754A08 X-CRM114-Status: GOOD ( 13.05 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Krzysztof Kozlowski , linux-samsung-soc@vger.kernel.org, Mauro Carvalho Chehab , Michael Turquette , Stephen Boyd , Shuah Khan , Tomasz Figa , Javier Martinez Canillas , Kukjin Kim , Sylwester Nawrocki , Nicolas Dufresne , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Marek Szyprowski MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The MFC IP is also inter-connected by an Async-Bridge so the CLK_ACLK333 has to be ungated during a power domain switch. Trying to do it when the clock is gated will fail and lead to an imprecise external abort error when the driver tries to access the MFC registers with the PD disabled. For example, if the s5p-mfc module is removed and the MFC PD turned off: [ 186.835606] Power domain power-domain@10044060 disable failed [ 186.835671] s5p-mfc 11000000.codec: Removing 11000000.codec [ 186.837670] Power domain power-domain@10044060 disable failed And when the module is inserted again: [ 2395.176956] s5p_mfc_wait_for_done_dev:34: Interrupt (dev->int_type:0, command:12) timed out [ 2395.177031] s5p_mfc_init_hw:272: Failed to load firmware [ 2395.177384] Unhandled fault: imprecise external abort (0x1406) at 0x00000000 [ 2395.177441] pgd = ec3b4000 [ 2395.177467] [00000000] *pgd=00000000 [ 2395.177507] Internal error: : 1406 [#1] PREEMPT SMP ARM [ 2395.177550] Modules linked in: s5p_mfc mwifiex_sdio mwifiex uvcvideo s5p_jpeg v4l2_mem2mem videobuf2_vmalloc videobuf2_dma_contig videobuf2_memops videobuf2_v4l2 videobuf2_core v4l2_common videodev media [last unloaded: s5p_mfc] [ 2395.177774] CPU: 1 PID: 2382 Comm: v4l_id Tainted: G W 4.6.0-rc6-next-20160502-00010-g7730dc64d2c1-dirty #179 [ 2395.177857] Hardware name: SAMSUNG EXYNOS (Flattened Device Tree) [ 2395.177906] task: ed275500 ti: e6c8c000 task.ti: e6c8c000 [ 2395.177996] PC is at s5p_mfc_reset+0x1c4/0x284 [s5p_mfc] [ 2395.178057] LR is at s5p_mfc_reset+0x1a4/0x284 [s5p_mfc] This patch fixes this issue by adding the CLK_ACLK333 as an Async-Bridge clock for the MFC power domain, so the PD configuration works properly. Signed-off-by: Javier Martinez Canillas Reviewed-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5420.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 4c8523471c65..f3e9d873633e 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -313,8 +313,9 @@ mfc_pd: power-domain@10044060 { compatible = "samsung,exynos4210-pd"; reg = <0x10044060 0x20>; - clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_USER_ACLK333>; - clock-names = "oscclk", "clk0"; + clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_USER_ACLK333>, + <&clock CLK_ACLK333>; + clock-names = "oscclk", "clk0","asb0"; #power-domain-cells = <0>; };