From patchwork Fri May 27 06:02:15 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Zhong X-Patchwork-Id: 9137671 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id A2E6E6075C for ; Fri, 27 May 2016 06:05:13 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9618227CEC for ; Fri, 27 May 2016 06:05:13 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 88F5028093; Fri, 27 May 2016 06:05:13 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 49E5827CEC for ; Fri, 27 May 2016 06:05:13 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1b6As8-0006hc-3Z; Fri, 27 May 2016 06:03:48 +0000 Received: from mail-pa0-f66.google.com ([209.85.220.66]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1b6Arm-0006WR-BW; Fri, 27 May 2016 06:03:27 +0000 Received: by mail-pa0-f66.google.com with SMTP id yl2so11394176pac.1; Thu, 26 May 2016 23:03:06 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=lkW5YuIhmzTBN1OLGn/C8tE9B3lgY2QvbnsZfgI7Z6c=; b=fB5Hmz5cv1jpYDdPpLAuMxqMvH5Idh9XYepXhGNI4l7xzESdVsZeSMSiPVKE0E4pTp 9FWgaHoohAGWqMIyJ+I67rZ+1aiM7s9FaYbUtl08lYNCvVFVz7SCavC2g7JtWIVuw82W YlVSDBpx4iE0doKcjwmfLVUE3wnISn2KQdVnhorzNMydIw4Wxh+VIOgR+C+Xc2qZWhoj vo6uPcofaa/ZhMYTguTIV8IiqPM4VXbSAZ45dvgcuOaEanXcpq9sX9L4Zg8kN4YcKFVy d/F+KPxYlBJ+MfmhQo0aEkoP8RBIaD7/F19eUGNFaJsMsN1UGT9SRpAnmoBfTOZRaew/ RDXA== X-Gm-Message-State: ALyK8tIz1If8AmDUX36S1JxUrOH65Sd28YLuptlWPNzV3NbD3vRFTbKLgC1QpkYXemmPZA== X-Received: by 10.66.73.193 with SMTP id n1mr19781723pav.70.1464328984646; Thu, 26 May 2016 23:03:04 -0700 (PDT) Received: from localhost.localdomain ([103.29.142.67]) by smtp.gmail.com with ESMTPSA id yp9sm24787497pab.42.2016.05.26.23.03.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 26 May 2016 23:03:03 -0700 (PDT) From: Chris Zhong To: dianders@chromium.org, tfiga@chromium.org, heiko@sntech.de, yzq@rock-chips.com Subject: [PATCH 2/6] Documentation: bindings: add dt doc for Rockchip USB Type-C PHY Date: Fri, 27 May 2016 14:02:15 +0800 Message-Id: <1464328939-8073-3-git-send-email-zyw@rock-chips.com> X-Mailer: git-send-email 2.6.3 In-Reply-To: <1464328939-8073-1-git-send-email-zyw@rock-chips.com> References: <1464328939-8073-1-git-send-email-zyw@rock-chips.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160526_230326_579297_007E1571 X-CRM114-Status: GOOD ( 12.65 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, Pawel Moll , Ian Campbell , linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, Rob Herring , Kumar Gala , Chris Zhong , linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds a binding that describes the Rockchip USB Type-C PHY for rk3399. Signed-off-by: Chris Zhong --- .../devicetree/bindings/phy/phy-rockchip-typec.txt | 55 ++++++++++++++++++++++ 1 file changed, 55 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt b/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt new file mode 100644 index 0000000..402f667 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt @@ -0,0 +1,55 @@ +ROCKCHIP type-c PHY + +Required properties: + - compatible: should be "rockchip,rk3399-typec-phy" + - reg : Address and length of the usb phy control register set + - rockchip,grf : phandle to the syscon managing the "general + register files" + - clocks : phandle + clock specifier for the phy clocks + - clock-names: string, clock name, must be "tcpdcore", "tcpdphy_ref"; + - resets : a list of phandle + reset specifier pairs + - reset-names : string reset name, must be: + "tcphy_rst", "tcphy_pipe_rst", "uphy_tcphy_rst" + - #phy-cells: Must be 0. See ./phy-bindings.txt for details. + - rockchip,usb3phy*: phy registers embed in grf + +Example: + tcphy0: phy@ff7c0000 { + compatible = "rockchip,rk3399-typec-phy"; + reg = <0x0 0xff7c0000 0x0 0x40000>; + #phy-cells = <0>; + rockchip,grf = <&grf>; + clocks = <&cru SCLK_UPHY0_TCPDCORE>, + <&cru SCLK_UPHY0_TCPDPHY_REF>; + clock-names = "tcpdcore", "tcpdphy_ref"; + resets = <&cru SRST_UPHY0>, + <&cru SRST_UPHY0_PIPE_L00>, + <&cru SRST_P_UPHY0_TCPHY>; + reset-names = "tcphy_rst", "tcphy_pipe_rst", "uphy_tcphy_rst"; + rockchip,usb3phy_con0 = <0x0e580 0 16>; + rockchip,usb3phy_con1 = <0x0e584 0 16>; + rockchip,usb3phy_con2 = <0x0e588 0 16>; + rockchip,usb3phy_status0 = <0x0e5c0 0 13>; + rockchip,usb3phy_status1 = <0x0e5c4 0 12>; + status = "disabled"; + }; + + tcphy1: phy@ff800000 { + compatible = "rockchip,rk3399-typec-phy"; + reg = <0x0 0xff800000 0x0 0x40000>; + #phy-cells = <0>; + rockchip,grf = <&grf>; + clocks = <&cru SCLK_UPHY1_TCPDCORE>, + <&cru SCLK_UPHY1_TCPDPHY_REF>; + clock-names = "tcpdcore", "tcpdphy_ref"; + resets = <&cru SRST_UPHY1>, + <&cru SRST_UPHY1_PIPE_L00>, + <&cru SRST_P_UPHY1_TCPHY>; + reset-names = "tcphy_rst", "tcphy_pipe_rst", "uphy_tcphy_rst"; + rockchip,usb3phy_con0 = <0x0e58c 0 16>; + rockchip,usb3phy_con1 = <0x0e590 0 16>; + rockchip,usb3phy_con2 = <0x0e594 0 16>; + rockchip,usb3phy_status0 = <0x0e5c0 16 13>; + rockchip,usb3phy_status1 = <0x0e5c4 16 12>; + status = "disabled"; + };