diff mbox

[2/5] arm/dts/imx6q-b850v3: Configure IPU assignment order

Message ID 1464626385-19253-3-git-send-email-peter.senna@collabora.com (mailing list archive)
State New, archived
Headers show

Commit Message

Peter Senna Tschudin May 30, 2016, 4:39 p.m. UTC
Configure the IPU assignment order to assign one IPU per external
display. A single IPU can drive multiple external displays but there are
resolution restrictions. After this patch the GPU is capalbe of driving two
Full-HD monitors.

Signed-off-by: Peter Senna Tschudin <peter.senna@collabora.com>
---
 arch/arm/boot/dts/imx6q-b850v3.dts | 5 +++++
 1 file changed, 5 insertions(+)

Comments

Fabio Estevam May 30, 2016, 4:49 p.m. UTC | #1
On Mon, May 30, 2016 at 1:39 PM, Peter Senna Tschudin
<peter.senna@collabora.com> wrote:
> Configure the IPU assignment order to assign one IPU per external
> display. A single IPU can drive multiple external displays but there are
> resolution restrictions. After this patch the GPU is capalbe of driving two

I think you meant "the IPU is capable"
Philipp Zabel June 2, 2016, 12:55 p.m. UTC | #2
Am Montag, den 30.05.2016, 18:39 +0200 schrieb Peter Senna Tschudin:
> Configure the IPU assignment order to assign one IPU per external
> display. A single IPU can drive multiple external displays but there are
> resolution restrictions. After this patch the GPU is capalbe of driving two
> Full-HD monitors.

It's also capable to do it before this patch, if you use the first and
third crtc. You are just reordering the crtcs.
Unfortunately the IPU has combined limitations across multiple crtcs in
one IPU, which currently can't be communicated to userspace.

regards
Philipp
diff mbox

Patch

diff --git a/arch/arm/boot/dts/imx6q-b850v3.dts b/arch/arm/boot/dts/imx6q-b850v3.dts
index 167f744..88a70de 100644
--- a/arch/arm/boot/dts/imx6q-b850v3.dts
+++ b/arch/arm/boot/dts/imx6q-b850v3.dts
@@ -51,6 +51,11 @@ 
 	chosen {
 		stdout-path = &uart3;
 	};
+
+	display-subsystem {
+		compatible = "fsl,imx-display-subsystem";
+		ports = <&ipu1_di0>, <&ipu2_di0>, <&ipu1_di1>, <&ipu2_di1>;
+	};
 };
 
 &clks {