From patchwork Thu Jun 9 22:23:31 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeremy Linton X-Patchwork-Id: 9168571 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 908C16048F for ; Thu, 9 Jun 2016 22:26:55 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8151728310 for ; Thu, 9 Jun 2016 22:26:55 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 7639D28359; Thu, 9 Jun 2016 22:26:55 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 1414628310 for ; Thu, 9 Jun 2016 22:26:55 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1bB8Nv-0001mN-5I; Thu, 09 Jun 2016 22:25:07 +0000 Received: from foss.arm.com ([217.140.101.70]) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1bB8N7-0000rM-5S for linux-arm-kernel@lists.infradead.org; Thu, 09 Jun 2016 22:24:19 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1522695D; Thu, 9 Jun 2016 15:24:14 -0700 (PDT) Received: from beelzebub.ast.arm.com (unknown [10.118.96.220]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 370CA3F213; Thu, 9 Jun 2016 15:23:37 -0700 (PDT) From: Jeremy Linton To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 6/8] arm64: pmu: Add routines for detecting differing PMU types in the system Date: Thu, 9 Jun 2016 17:23:31 -0500 Message-Id: <1465511013-10742-7-git-send-email-jeremy.linton@arm.com> X-Mailer: git-send-email 2.5.5 In-Reply-To: <1465511013-10742-1-git-send-email-jeremy.linton@arm.com> References: <1465511013-10742-1-git-send-email-jeremy.linton@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160609_152417_378138_3A0E5CCB X-CRM114-Status: GOOD ( 17.00 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, lorenzo.pieralisi@arm.com, mlangsdorf@redhat.com, peterz@infradead.org, catalin.marinas@arm.com, will.deacon@arm.com, acme@kernel.org, linux-acpi@vger.kernel.org, alexander.shishkin@linux.intel.com, mingo@redhat.com MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP In preparation for enabling heterogeneous PMUs on ACPI systems add routines that detect this and group the resulting PMUs and interrupts. Signed-off-by: Jeremy Linton --- drivers/perf/arm_pmu_acpi.c | 135 +++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 132 insertions(+), 3 deletions(-) diff --git a/drivers/perf/arm_pmu_acpi.c b/drivers/perf/arm_pmu_acpi.c index 98c452d..a257fc0 100644 --- a/drivers/perf/arm_pmu_acpi.c +++ b/drivers/perf/arm_pmu_acpi.c @@ -1,14 +1,19 @@ /* - * PMU support + * ARM ACPI PMU support * * Copyright (C) 2015 Red Hat Inc. + * Copyright (C) 2016 ARM Ltd. * Author: Mark Salter + * Jeremy Linton * * This work is licensed under the terms of the GNU GPL, version 2. See * the COPYING file in the top-level directory. * */ +#define pr_fmt(fmt) "ACPI-PMU: " fmt + +#include #include #include #include @@ -18,8 +23,14 @@ #define PMU_PDEV_NAME "armv8-pmu" struct pmu_irq { - int gsi; - int trigger; + int gsi; + int trigger; + bool registered; +}; + +struct pmu_types { + int cpu_type; + int cpu_count; }; static struct pmu_irq pmu_irqs[NR_CPUS] __initdata; @@ -31,6 +42,124 @@ void __init arm_pmu_parse_acpi(int cpu, struct acpi_madt_generic_interrupt *gic) pmu_irqs[cpu].trigger = ACPI_EDGE_SENSITIVE; else pmu_irqs[cpu].trigger = ACPI_LEVEL_SENSITIVE; + pr_devel("Assign CPU %d girq %d level %d\n", cpu, pmu_irqs[cpu].gsi, + pmu_irqs[cpu].trigger); +} + +/* Count number and type of CPU cores in the system. */ +void __init arm_pmu_acpi_determine_cpu_types(struct pmu_types *pmus) +{ + int i, j; + + for_each_possible_cpu(i) { + struct cpuinfo_arm64 *cinfo = per_cpu_ptr(&cpu_data, i); + u32 partnum = MIDR_PARTNUM(cinfo->reg_midr); + + pr_devel("Present CPU %d is a %X\n", i, partnum); + for (j = 0; j < num_possible_cpus(); j++) { + if (pmus[j].cpu_type == partnum) { + pmus[j].cpu_count++; + break; + } + if (pmus[j].cpu_count == 0) { + pmus[j].cpu_type = partnum; + pmus[j].cpu_count++; + break; + } + } + } +} + +/* + * Registers the group of PMU interfaces which corrispond to the 'last_cpu_id'. + * This group utlizes 'count' resources in the 'res'. + */ +int __init arm_pmu_acpi_register_pmu(int count, struct resource *res, + int last_cpu_id) +{ + int i; + int err = -ENOMEM; + bool free_gsi = false; + struct platform_device *pdev; + + if (count) { + pdev = platform_device_alloc(PMU_PDEV_NAME, last_cpu_id); + if (pdev) { + err = platform_device_add_resources(pdev, + res, count); + if (!err) { + err = platform_device_add(pdev); + if (err) { + pr_warn("Unable to register PMU device\n"); + free_gsi = true; + } + } else { + pr_warn("Unable to add resources to device\n"); + free_gsi = true; + platform_device_put(pdev); + } + } else { + pr_warn("Unable to allocate platform device\n"); + free_gsi = true; + } + } + + /* unmark (and possibly unregister) registered GSIs */ + for_each_possible_cpu(i) { + if (pmu_irqs[i].registered) { + if (free_gsi) + acpi_unregister_gsi(pmu_irqs[i].gsi); + pmu_irqs[i].registered = false; + } + } + + return err; +} + +/* + * For the given cpu/pmu type, walk all known GSIs, register them, and add + * them to the resource structure. Return the number of GSI's contained + * in the res structure, and the id of the last CPU/PMU we added. + */ +int __init arm_pmu_acpi_gsi_res(struct pmu_types *pmus, + struct resource *res, int *last_cpu_id) +{ + int i, count; + int irq; + + pr_info("Setting up %d PMUs for CPU type %X\n", pmus->cpu_count, + pmus->cpu_type); + /* lets group all the PMU's from similar CPU's together */ + count = 0; + for_each_possible_cpu(i) { + struct cpuinfo_arm64 *cinfo = per_cpu_ptr(&cpu_data, i); + + if (pmus->cpu_type == MIDR_PARTNUM(cinfo->reg_midr)) { + pr_devel("Setting up CPU %d\n", i); + if (pmu_irqs[i].gsi == 0) + continue; + + irq = acpi_register_gsi(NULL, pmu_irqs[i].gsi, + pmu_irqs[i].trigger, + ACPI_ACTIVE_HIGH); + + res[count].start = res[count].end = irq; + res[count].flags = IORESOURCE_IRQ; + + if (pmu_irqs[i].trigger == ACPI_EDGE_SENSITIVE) + res[count].flags |= IORESOURCE_IRQ_HIGHEDGE; + else + res[count].flags |= IORESOURCE_IRQ_HIGHLEVEL; + + pmu_irqs[i].registered = true; + count++; + (*last_cpu_id) = cinfo->reg_midr; + + if (irq_is_percpu(irq)) + pr_debug("PPI detected\n"); + } + } + return count; } static int __init pmu_acpi_init(void)