From patchwork Mon Jun 13 15:03:01 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vladimir Murzin X-Patchwork-Id: 9173353 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id E17F96075D for ; Mon, 13 Jun 2016 15:06:52 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D25E420499 for ; Mon, 13 Jun 2016 15:06:52 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C755625EF7; Mon, 13 Jun 2016 15:06:52 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 69BD720499 for ; Mon, 13 Jun 2016 15:06:52 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1bCTPL-0004R5-2o; Mon, 13 Jun 2016 15:04:07 +0000 Received: from foss.arm.com ([217.140.101.70]) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1bCTP7-0004HG-7b for linux-arm-kernel@lists.infradead.org; Mon, 13 Jun 2016 15:03:54 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 842E03A8; Mon, 13 Jun 2016 08:04:15 -0700 (PDT) Received: from bc-c5-1-15.euhpc.arm.com. (bc-c5-1-15.euhpc.arm.com [10.6.16.35]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id BA8673F253; Mon, 13 Jun 2016 08:03:34 -0700 (PDT) From: Vladimir Murzin To: linux@arm.linux.org.uk Subject: [PATCH 02/10] ARM: V7M: Make read_cpuid() generally available on V7M. Date: Mon, 13 Jun 2016 16:03:01 +0100 Message-Id: <1465830189-20128-3-git-send-email-vladimir.murzin@arm.com> X-Mailer: git-send-email 2.0.0 In-Reply-To: <1465830189-20128-1-git-send-email-vladimir.murzin@arm.com> References: <1465830189-20128-1-git-send-email-vladimir.murzin@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160613_080353_443858_A6C5D094 X-CRM114-Status: UNSURE ( 9.65 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kernel@pengutronix.de, manabian@gmail.com, stefan@agner.ch, kbuild-all@01.org, mcoquelin.stm32@gmail.com, alexandre.torgue@gmail.com, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Jonathan Austin Previously V7M had a custom definition for read_cpuid_id that didn't use the underlying read_cpuid() macro and a stub definition for read_cpuid(). This requires a custom specialisation for each of the CPUID_* registers, and as more than just CPUID_ID may be implemented in the future this doesn't make much sense. This patch creates a generic implementation of read_cpuid for V7M and removes the custom read_cpuid_id implementation. Signed-off-by: Jonathan Austin Signed-off-by: Vladimir Murzin --- arch/arm/include/asm/cputype.h | 50 ++++++++++++++++++++++------------------ 1 file changed, 28 insertions(+), 22 deletions(-) diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h index 1ee94c7..a689034 100644 --- a/arch/arm/include/asm/cputype.h +++ b/arch/arm/include/asm/cputype.h @@ -4,15 +4,15 @@ #include #include -#define CPUID_ID 0 -#define CPUID_CACHETYPE 1 -#define CPUID_TCM 2 -#define CPUID_TLBTYPE 3 -#define CPUID_MPUIR 4 -#define CPUID_MPIDR 5 -#define CPUID_REVIDR 6 - #ifdef CONFIG_CPU_V7M + +#define CPUID_ID 0x0 +#define CPUID_CACHETYPE -1 +#define CPUID_TCM -1 +#define CPUID_TLBTYPE -1 +#define CPUID_MPIDR -1 +#define CPUID_REVIDR -1 + #define CPUID_EXT_PFR0 0x40 #define CPUID_EXT_PFR1 0x44 #define CPUID_EXT_DFR0 0x48 @@ -28,6 +28,14 @@ #define CPUID_EXT_ISAR4 0x70 #define CPUID_EXT_ISAR5 0x74 #else +#define CPUID_ID 0 +#define CPUID_CACHETYPE 1 +#define CPUID_TCM 2 +#define CPUID_TLBTYPE 3 +#define CPUID_MPUIR 4 +#define CPUID_MPIDR 5 +#define CPUID_REVIDR 6 + #define CPUID_EXT_PFR0 "c1, 0" #define CPUID_EXT_PFR1 "c1, 1" #define CPUID_EXT_DFR0 "c1, 2" @@ -114,11 +122,16 @@ extern unsigned int processor_id; #include #include -#define read_cpuid(reg) \ - ({ \ - WARN_ON_ONCE(1); \ - 0; \ - }) +static inline unsigned int __attribute_const__ read_cpuid(unsigned offset) +{ + switch (offset) { + case CPUID_ID: + return readl(BASEADDR_V7M_SCB + offset); + default: + WARN_ON_ONCE(1); + return 0; + } +} static inline unsigned int __attribute_const__ read_cpuid_ext(unsigned offset) { @@ -141,7 +154,7 @@ static inline unsigned int __attribute_const__ read_cpuid_ext(unsigned offset) #endif /* ifdef CONFIG_CPU_CP15 / else */ -#ifdef CONFIG_CPU_CP15 +#if defined(CONFIG_CPU_CP15) || defined(CONFIG_CPU_V7M) /* * The CPU ID never changes at run time, so we might as well tell the * compiler that it's constant. Use this function to read the CPU ID @@ -152,14 +165,7 @@ static inline unsigned int __attribute_const__ read_cpuid_id(void) return read_cpuid(CPUID_ID); } -#elif defined(CONFIG_CPU_V7M) - -static inline unsigned int __attribute_const__ read_cpuid_id(void) -{ - return readl(BASEADDR_V7M_SCB + V7M_SCB_CPUID); -} - -#else /* ifdef CONFIG_CPU_CP15 / elif defined(CONFIG_CPU_V7M) */ +#else /* if defined(CONFIG_CPU_CP15) || defined(CONFIG_CPU_V7M) */ static inline unsigned int __attribute_const__ read_cpuid_id(void) {