From patchwork Tue Jun 14 18:00:35 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laura Abbott X-Patchwork-Id: 9176381 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id A4D8F60772 for ; Tue, 14 Jun 2016 18:02:25 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9939F265B9 for ; Tue, 14 Jun 2016 18:02:25 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8DE6628236; Tue, 14 Jun 2016 18:02:25 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.8 required=2.0 tests=BAYES_00,HEXHASH_WORD, RCVD_IN_DNSWL_MED autolearn=no version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 28E79265B9 for ; Tue, 14 Jun 2016 18:02:25 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1bCseB-0006vF-4X; Tue, 14 Jun 2016 18:01:07 +0000 Received: from mail-qg0-f51.google.com ([209.85.192.51]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1bCse7-0006ke-R9 for linux-arm-kernel@lists.infradead.org; Tue, 14 Jun 2016 18:01:05 +0000 Received: by mail-qg0-f51.google.com with SMTP id v48so71131878qgd.2 for ; Tue, 14 Jun 2016 11:00:43 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=7R4l3ZXlHcESnfhFJoMC8chFMXyG4cURtJ6k21/P5h8=; b=H4xq0XZjYRMW0Q/c00N2jUfrdCS/XHOImIpVE3I/HXqf54JImzAU9FLV572EHq7C9x yJU54GevHwkmXPLwhbJNj/YlL76am0NryDtkoJ5O+ry9eIuc1zUV4DAQX5JAX9Sr5TzZ x8jWjeoWrWMs/Z4L8fmkaHqpvJYshKDp+OjuFhWVup3T1q3WT0s5RCt/DofBD6bnXl43 nky9rJBNI9B0xh0ssikzo5ILq3jPv9UqtJADVa9m9+jNmDSVGniC0fTSKD/Bs3bKirsu rxRwLm9qf2TRb4WnzfE4KPjq78hrpV9I4LliIKGveo4SnkZxH/Pw5xCelIM+1ZLu1cJE JLnw== X-Gm-Message-State: ALyK8tKaCPJTYz5CurpY7i4Up5HbX5Szap1NI/jDfU6/aWwSA7wRA8clrcvpHvZSYTDBo7w5 X-Received: by 10.140.153.135 with SMTP id 129mr21555564qhz.71.1465927242203; Tue, 14 Jun 2016 11:00:42 -0700 (PDT) Received: from labbott-redhat-machine.redhat.com ([2601:602:9800:177f::337f]) by smtp.gmail.com with ESMTPSA id s132sm5797113qha.14.2016.06.14.11.00.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 14 Jun 2016 11:00:40 -0700 (PDT) From: Laura Abbott To: Ard Biesheuvel , Mark Rutland , Will Deacon , Catalin Marinas Subject: [PATCHv2] arm64: Handle el1 synchronous instruction aborts cleanly Date: Tue, 14 Jun 2016 11:00:35 -0700 Message-Id: <1465927235-8163-1-git-send-email-labbott@redhat.com> X-Mailer: git-send-email 2.5.5 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160614_110103_965235_036AB50B X-CRM114-Status: GOOD ( 12.13 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laura Abbott , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Executing from a non-executable area gives an ugly message: lkdtm: Performing direct entry EXEC_RODATA lkdtm: attempting ok execution at ffff0000084c0e08 lkdtm: attempting bad execution at ffff000008880700 Bad mode in Synchronous Abort handler detected on CPU2, code 0x8400000e -- IABT (current EL) CPU: 2 PID: 998 Comm: sh Not tainted 4.7.0-rc2+ #13 Hardware name: linux,dummy-virt (DT) task: ffff800077e35780 ti: ffff800077970000 task.ti: ffff800077970000 PC is at lkdtm_rodata_do_nothing+0x0/0x8 LR is at execute_location+0x74/0x88 The 'IABT (current EL)' indicates the error but it's a bit cryptic without knowledge of the ARM ARM. There is also no indication of the specific address which triggered the fault. The increase in kernel page permissions makes hitting this case more likely as well. Handling the case in the vectors gives a much more familiar looking error message: lkdtm: Performing direct entry EXEC_RODATA lkdtm: attempting ok execution at ffff0000084c0840 lkdtm: attempting bad execution at ffff000008880680 Unable to handle kernel paging request at virtual address ffff000008880680 pgd = ffff8000089b2000 [ffff000008880680] *pgd=00000000489b4003, *pud=0000000048904003, *pmd=0000000000000000 Internal error: Oops: 8400000e [#1] PREEMPT SMP Modules linked in: CPU: 1 PID: 997 Comm: sh Not tainted 4.7.0-rc1+ #24 Hardware name: linux,dummy-virt (DT) task: ffff800077f9f080 ti: ffff800008a1c000 task.ti: ffff800008a1c000 PC is at lkdtm_rodata_do_nothing+0x0/0x8 LR is at execute_location+0x74/0x88 Acked-by: Mark Rutland Signed-off-by: Laura Abbott --- v2: Clarified the messages we got a bit. Verified this applies cleanly on top of Mark Rutland's kill-esr-lnx-exec series --- arch/arm64/kernel/entry.S | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S index eefffa8..6c6cec9 100644 --- a/arch/arm64/kernel/entry.S +++ b/arch/arm64/kernel/entry.S @@ -336,6 +336,8 @@ el1_sync: lsr x24, x1, #ESR_ELx_EC_SHIFT // exception class cmp x24, #ESR_ELx_EC_DABT_CUR // data abort in EL1 b.eq el1_da + cmp x24, #ESR_ELx_EC_IABT_CUR // instruction abort in EL1 + b.eq el1_ia cmp x24, #ESR_ELx_EC_SYS64 // configurable trap b.eq el1_undef cmp x24, #ESR_ELx_EC_SP_ALIGN // stack alignment exception @@ -347,6 +349,23 @@ el1_sync: cmp x24, #ESR_ELx_EC_BREAKPT_CUR // debug exception in EL1 b.ge el1_dbg b el1_inv +el1_ia: + /* + * Instruction abort handling + */ + mrs x0, far_el1 + enable_dbg + // re-enable interrupts if they were enabled in the aborted context + tbnz x23, #7, 1f // PSR_I_BIT + enable_irq + orr x1, x1, #1 << 24 // use reserved ISS bit for instruction aborts +1: + mov x2, sp // struct pt_regs + bl do_mem_abort + + // disable interrupts before pulling preserved data off the stack + disable_irq + kernel_exit 1 el1_da: /* * Data abort handling