[RFC] can: c_can: Update D_CAN TX and RX functions to 32 bit.

Commit Message

[e-mail] June 16, 2016, 4:10 p.m. UTC

From: Thor Thayer <[e-mail]>

When testing CAN write floods on Altera's CycloneV, the
first 2 bytes are sometimes 0x00, 0x00 or corrupted
instead of the values sent. Also observed bytes 4 & 5
were corrupted in some cases.

The D_CAN Data registers are 32 bits and changing from
16 bit writes to 32 bit writes fixes the problem.

Testing performed on Altera CycloneV (D_CAN).
Requesting tests on other C_CAN & D_CAN platforms.

Reported-by: Richard Andrysek <[e-mail]>
Signed-off-by: Thor Thayer <[e-mail]>
---
 drivers/net/can/c_can/c_can.c |   38 +++++++++++++++++++++++++++++++-------
 1 file changed, 31 insertions(+), 7 deletions(-)

Comments

Marc Kleine-Budde June 17, 2016, 9:04 a.m. UTC | #1

On 06/16/2016 06:10 PM, [e-mail] wrote:
> From: Thor Thayer <[e-mail]>
> 
> When testing CAN write floods on Altera's CycloneV, the
> first 2 bytes are sometimes 0x00, 0x00 or corrupted
> instead of the values sent. Also observed bytes 4 & 5
> were corrupted in some cases.
> 
> The D_CAN Data registers are 32 bits and changing from
> 16 bit writes to 32 bit writes fixes the problem.
> 
> Testing performed on Altera CycloneV (D_CAN).
> Requesting tests on other C_CAN & D_CAN platforms.
> 
> Reported-by: Richard Andrysek <[e-mail]>
> Signed-off-by: Thor Thayer <[e-mail]>

Applied to can with stable on Cc.

Marc

Richard Andrysek June 22, 2016, 6:43 p.m. UTC | #2

Sorry for a delay. I've run my test with 16 messages per channel (can0, can1 concurrently) with a cycle time 2.8ms, 1Mbps. And it works now properly.

Thank you all participated on this issue

Richard

-----Ursprüngliche Nachricht-----
Von: Marc Kleine-Budde [mailto:[e-mail]] 
Gesendet: Freitag, 17. Juni 2016 11:04
An: [e-mail]; [e-mail]; [e-mail]; Richard Andrysek <[e-mail]>
Cc: [e-mail]; [e-mail]; [e-mail]; [e-mail]
Betreff: Re: [RFC] can: c_can: Update D_CAN TX and RX functions to 32 bit.

On 06/16/2016 06:10 PM, [e-mail] wrote:
> From: Thor Thayer <[e-mail]>

> 

> When testing CAN write floods on Altera's CycloneV, the first 2 bytes 

> are sometimes 0x00, 0x00 or corrupted instead of the values sent. Also 

> observed bytes 4 & 5 were corrupted in some cases.

> 

> The D_CAN Data registers are 32 bits and changing from

> 16 bit writes to 32 bit writes fixes the problem.

> 

> Testing performed on Altera CycloneV (D_CAN).

> Requesting tests on other C_CAN & D_CAN platforms.

> 

> Reported-by: Richard Andrysek <[e-mail]>

> Signed-off-by: Thor Thayer <[e-mail]>


Applied to can with stable on Cc.

Marc

-- 
Pengutronix e.K.                  | Marc Kleine-Budde           |
Industrial Linux Solutions        | Phone: [phone]     |
Vertretung West/Dortmund          | Fax:   [phone]-5555 |
Amtsgericht Hildesheim, HRA 2686  | http://www.pengutronix.de   |

Patch

diff --git a/drivers/net/can/c_can/c_can.c b/drivers/net/can/c_can/c_can.c
index f91b094..e3dccd3 100644
--- a/drivers/net/can/c_can/c_can.c
+++ b/drivers/net/can/c_can/c_can.c
@@ -332,9 +332,23 @@  static void c_can_setup_tx_object(struct net_device *dev, int iface,
 
 	priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), ctrl);
 
-	for (i = 0; i < frame->can_dlc; i += 2) {
-		priv->write_reg(priv, C_CAN_IFACE(DATA1_REG, iface) + i / 2,
-				frame->data[i] | (frame->data[i + 1] << 8));
+	if (priv->type == BOSCH_D_CAN) {
+		u32 data = 0, dreg = C_CAN_IFACE(DATA1_REG, iface);
+
+		for (i = 0; i < frame->can_dlc; i += 4, dreg += 2) {
+			data = (u32)frame->data[i];
+			data |= (u32)frame->data[i + 1] << 8;
+			data |= (u32)frame->data[i + 2] << 16;
+			data |= (u32)frame->data[i + 3] << 24;
+			priv->write_reg32(priv, dreg, data);
+		}
+	} else {
+		for (i = 0; i < frame->can_dlc; i += 2) {
+			priv->write_reg(priv,
+					C_CAN_IFACE(DATA1_REG, iface) + i / 2,
+					frame->data[i] |
+					(frame->data[i + 1] << 8));
+		}
 	}
 }
 
@@ -402,10 +416,20 @@  static int c_can_read_msg_object(struct net_device *dev, int iface, u32 ctrl)
 	} else {
 		int i, dreg = C_CAN_IFACE(DATA1_REG, iface);
 
-		for (i = 0; i < frame->can_dlc; i += 2, dreg ++) {
-			data = priv->read_reg(priv, dreg);
-			frame->data[i] = data;
-			frame->data[i + 1] = data >> 8;
+		if (priv->type == BOSCH_D_CAN) {
+			for (i = 0; i < frame->can_dlc; i += 4, dreg += 2) {
+				data = priv->read_reg32(priv, dreg);
+				frame->data[i] = data;
+				frame->data[i + 1] = data >> 8;
+				frame->data[i + 2] = data >> 16;
+				frame->data[i + 3] = data >> 24;
+			}
+		} else {
+			for (i = 0; i < frame->can_dlc; i += 2, dreg++) {
+				data = priv->read_reg(priv, dreg);
+				frame->data[i] = data;
+				frame->data[i + 1] = data >> 8;
+			}
 		}
 	}