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[92.17.247.99]) by smtp.gmail.com with ESMTPSA id o129sm4240934wmb.17.2016.06.17.08.14.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 17 Jun 2016 08:14:39 -0700 (PDT) From: Srinivas Kandagatla To: Andy Gross Subject: [PATCH 11/16] arm64: dts: msm8996: add support to blsp1_spi0 pinctrl Date: Fri, 17 Jun 2016 16:14:08 +0100 Message-Id: <1466176454-28084-12-git-send-email-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1466176454-28084-1-git-send-email-srinivas.kandagatla@linaro.org> References: <1466176454-28084-1-git-send-email-srinivas.kandagatla@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160617_081502_577663_9B2049E0 X-CRM114-Status: GOOD ( 10.29 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, David Brown , Rob Herring , Srinivas Kandagatla , linux-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds pinctrl nodes required for blsp1_spi0. Signed-off-by: Srinivas Kandagatla --- arch/arm64/boot/dts/qcom/msm8996-pins.dtsi | 34 ++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi index 79ed98c..9fd37a0 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi @@ -13,6 +13,40 @@ &msmgpio { + blsp1_spi0_default: blsp1_spi0_default { + pinmux { + function = "blsp_spi1"; + pins = "gpio0", "gpio1", "gpio3"; + }; + pinmux_cs { + function = "gpio"; + pins = "gpio2"; + }; + pinconf { + pins = "gpio0", "gpio1", "gpio3"; + drive-strength = <12>; + bias-disable; + }; + pinconf_cs { + pins = "gpio2"; + drive-strength = <16>; + bias-disable; + output-high; + }; + }; + + blsp1_spi0_sleep: blsp1_spi0_sleep { + pinmux { + function = "gpio"; + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + }; + pinconf { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + drive-strength = <2>; + bias-pull-down; + }; + }; + blsp1_i2c2_default: blsp1_i2c2_default { pinmux { function = "blsp_i2c3";