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[73.225.163.254]) by smtp.gmail.com with ESMTPSA id uj5sm56195069pac.28.2016.06.18.17.31.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 18 Jun 2016 17:31:26 -0700 (PDT) From: Andrey Smirnov To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 1/5] i.MX: system.c: Convert goto to if statement Date: Sat, 18 Jun 2016 17:31:03 -0700 Message-Id: <1466296268-27099-3-git-send-email-andrew.smirnov@gmail.com> X-Mailer: git-send-email 2.5.5 In-Reply-To: <1466296268-27099-1-git-send-email-andrew.smirnov@gmail.com> References: <1466296268-27099-1-git-send-email-andrew.smirnov@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160618_173149_424282_01BE899D X-CRM114-Status: GOOD ( 13.58 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Russell King , Arnd Bergmann , Andrey Smirnov , linux-kernel@vger.kernel.org, Sascha Hauer , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Shawn Guo MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Using goto here doesn't bring any advantages and only makes the code flow less clear. No functional changes. Acked-by: Arnd Bergmann Signed-off-by: Andrey Smirnov --- arch/arm/mach-imx/system.c | 36 +++++++++++++++++------------------- 1 file changed, 17 insertions(+), 19 deletions(-) diff --git a/arch/arm/mach-imx/system.c b/arch/arm/mach-imx/system.c index 105d1ce..d9f8b0e 100644 --- a/arch/arm/mach-imx/system.c +++ b/arch/arm/mach-imx/system.c @@ -106,26 +106,24 @@ void __init imx_init_l2cache(void) goto out; } - if (readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN) - goto skip_if_enabled; - - /* Configure the L2 PREFETCH and POWER registers */ - val = readl_relaxed(l2x0_base + L310_PREFETCH_CTRL); - val |= 0x70800000; - /* - * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0 - * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2 - * But according to ARM PL310 errata: 752271 - * ID: 752271: Double linefill feature can cause data corruption - * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2 - * Workaround: The only workaround to this erratum is to disable the - * double linefill feature. This is the default behavior. - */ - if (cpu_is_imx6q()) - val &= ~(1 << 30 | 1 << 23); - writel_relaxed(val, l2x0_base + L310_PREFETCH_CTRL); + if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) { + /* Configure the L2 PREFETCH and POWER registers */ + val = readl_relaxed(l2x0_base + L310_PREFETCH_CTRL); + val |= 0x70800000; + /* + * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0 + * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2 + * But according to ARM PL310 errata: 752271 + * ID: 752271: Double linefill feature can cause data corruption + * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2 + * Workaround: The only workaround to this erratum is to disable the + * double linefill feature. This is the default behavior. + */ + if (cpu_is_imx6q()) + val &= ~(1 << 30 | 1 << 23); + writel_relaxed(val, l2x0_base + L310_PREFETCH_CTRL); + } -skip_if_enabled: iounmap(l2x0_base); of_node_put(np);