From patchwork Mon Jun 20 17:56:51 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 9188413 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 3A544607D1 for ; Mon, 20 Jun 2016 18:06:05 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2F03027BFC for ; Mon, 20 Jun 2016 18:06:05 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2297827C14; Mon, 20 Jun 2016 18:06:05 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED, T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id BD2F527BFC for ; Mon, 20 Jun 2016 18:06:04 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.85_2 #1 (Red Hat Linux)) id 1bF3Ym-0004My-0W; Mon, 20 Jun 2016 18:04:32 +0000 Received: from casper.infradead.org ([2001:770:15f::2]) by bombadil.infradead.org with esmtps (Exim 4.85_2 #1 (Red Hat Linux)) id 1bF3Ve-0007N1-6b for linux-arm-kernel@bombadil.infradead.org; Mon, 20 Jun 2016 18:01:18 +0000 Received: from mail-pf0-x234.google.com ([2607:f8b0:400e:c00::234]) by casper.infradead.org with esmtps (Exim 4.85_2 #1 (Red Hat Linux)) id 1bF3Vb-00012V-BP for linux-arm-kernel@lists.infradead.org; Mon, 20 Jun 2016 18:01:16 +0000 Received: by mail-pf0-x234.google.com with SMTP id h14so41119519pfe.1 for ; Mon, 20 Jun 2016 11:00:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=eEkXeOSOWNH4XIKvbY/UwBnDZQOA6CSJ3SmXOac8UPQ=; b=SM4s3TjzrsUlR7ZOBb7NjhpA92lc9//brkblrZnnEF4mmhaB+99pdZulyHlld11kVg jH5zpBTVy5Sj+RHx9+btwYOBgpFN6ZDX5w9K6SA70jM5rQRDdoO+9pRNa4ssrWJzb5Ai JJs8yZK6C0s3u+eIExn+frxcMhvNOP2xN5/b0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=eEkXeOSOWNH4XIKvbY/UwBnDZQOA6CSJ3SmXOac8UPQ=; b=c1McXcpCbYBpJxNsCu+WmpUTqfq/j3Of01C4w/MSVsX8eb3/B7iqgbms922sUD15eu fn5D8TXbAHUYWGhnCdAuGIBCFLB0O7nUD75Vxx7eyijPSQa2VlU5ZO4Uwqsn+7TwnXxV BnoNAQ5pamoNQxwB5Q8+aSBUEgLkmGB3jxxW18g8/yH50s2BLKaiM0f2WwA97jlclJqT MqpLB7jmxscc0/Js//qukrVa5RRem4o+IfmwXr0CrIlW9sqBHsyToxZbgncwV+9zssR5 yUlHJhpfgnKiYk35inPvrcfkHme+AaqJilpxM/wZHV4COAG8Qd/zXg6oKVSpkgeQOVWg 8w3Q== X-Gm-Message-State: ALyK8tJqsXbHKRe1vCNQxZyeYXZUVUy8Gy3l7Ewd+nAONz6+pkM6CZNkm54tv7pZwSYMjyYU X-Received: by 10.98.192.12 with SMTP id x12mr22954569pff.106.1466445652742; Mon, 20 Jun 2016 11:00:52 -0700 (PDT) Received: from tictac.mtv.corp.google.com ([172.22.65.76]) by smtp.gmail.com with ESMTPSA id c189sm60250353pfg.19.2016.06.20.11.00.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 20 Jun 2016 11:00:51 -0700 (PDT) From: Douglas Anderson To: ulf.hansson@linaro.org, Heiko Stuebner Subject: [PATCH v3 12/15] Documentation: phy: Let the rockchip eMMC PHY get an exported card clock Date: Mon, 20 Jun 2016 10:56:51 -0700 Message-Id: <1466445414-11974-13-git-send-email-dianders@chromium.org> X-Mailer: git-send-email 2.8.0.rc3.226.g39d4020 In-Reply-To: <1466445414-11974-1-git-send-email-dianders@chromium.org> References: <1466445414-11974-1-git-send-email-dianders@chromium.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160620_190115_562159_80ABEC66 X-CRM114-Status: GOOD ( 14.12 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Douglas Anderson , devicetree@vger.kernel.org, xzy.xu@rock-chips.com, pawel.moll@arm.com, ijc+devicetree@hellion.org.uk, linux-kernel@vger.kernel.org, shawn.lin@rock-chips.com, briannorris@chromium.org, linux-mmc@vger.kernel.org, adrian.hunter@intel.com, kishon@ti.com, linux-rockchip@lists.infradead.org, robh+dt@kernel.org, galak@codeaurora.org, groeck@chromium.org, mark.rutland@arm.com, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP As of an earlier change in this series ("Documentation: mmc: sdhci-of-arasan: Add ability to export card clock") the SDHCI driver used on Rockchip SoCs can now expose its clock. Let's now specify that the PHY can use it. Letting the PHY get access to this clock means it can adjust phyctrl_frqsel field appropriately. Although the Rockchip PHY appears slightly different than the reference Arasan one, you can see that the Arasan datasheet [1] had it defined as: Select the frequency range of DLL operation: 3b'000 => 200MHz to 170 MHz 3b'001 => 170MHz to 140 MHz 3b'010 => 140MHz to 110 MHz 3b'011 => 110MHz to 80MHz 3b'100 => 80MHz to 50 MHz 3b'101 => 275Mhz to 250MHz 3b'110 => 250MHz to 225MHz 3b'111 => 225MHz to 200MHz On the Rockchip version of the PHY we have less granularity but the idea is the same. [1]: https://arasan.com/wp-content/media/eMMC-5-1-Total-Solution_Rev-1-3.pdf Signed-off-by: Douglas Anderson Acked-by: Kishon Vijay Abraham I Acked-by: Rob Herring Reviewed-by: Heiko Stuebner --- Changes in v3: - Add collected tags Changes in v2: - List out clocks and clock names (Rob) Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt b/Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt index 555cb0f40690..e3ea55763b0a 100644 --- a/Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt +++ b/Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt @@ -7,6 +7,13 @@ Required properties: - reg: PHY register address offset and length in "general register files" +Optional clocks using the clock bindings (see ../clock/clock-bindings.txt), +specified by name: + - clock-names: Should contain "emmcclk". Although this is listed as optional + (because most boards can get basic functionality without having + access to it), it is strongly suggested. + - clocks: Should have a phandle to the card clock exported by the SDHCI driver. + Example: @@ -20,6 +27,8 @@ grf: syscon@ff770000 { emmcphy: phy@f780 { compatible = "rockchip,rk3399-emmc-phy"; reg = <0xf780 0x20>; + clocks = <&sdhci>; + clock-names = "emmcclk"; #phy-cells = <0>; }; };