| Message ID | 1466484811-26923-2-git-send-email-zhengxing@rock-chips.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Hi,
[auto build test ERROR on rockchip/for-next]
[also build test ERROR on v4.7-rc4 next-20160621]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Xing-Zheng/Fix-and-improve-clock-controller-for-the-RK322x-SoCs/20160621-130641
base: https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git for-next
config: arm64-defconfig (attached as .config)
compiler: aarch64-linux-gnu-gcc (Debian 5.3.1-8) 5.3.1 20160205
reproduce:
wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=arm64
Note: the linux-review/Xing-Zheng/Fix-and-improve-clock-controller-for-the-RK322x-SoCs/20160621-130641 HEAD 46fe9dec31bc488791124a6237caa95c0cd75a30 builds fine.
It only hurts bisectibility.
All error/warnings (new ones prefixed by >>):
>> drivers/clk/rockchip/clk-rk3228.c:667:0: error: unterminated argument list invoking macro "COMPOSITE_FRAC"
CLK_OF_DECLARE(rk3228_cru, "rockchip,rk3228-cru", rk3228_clk_init);
^
>> drivers/clk/rockchip/clk-rk3228.c:392:2: error: 'COMPOSITE_FRAC' undeclared here (not in a function)
COMPOSITE_FRAC(0, "i2s1_frac", "i2s1_src", CLK_SET_RATE_PARENT,
^
>> drivers/clk/rockchip/clk-rk3228.c:392:2: error: expected '}' at end of input
>> drivers/clk/rockchip/clk-rk3228.c:104:42: warning: 'rk3228_cpuclk_rates' defined but not used [-Wunused-variable]
static struct rockchip_cpuclk_rate_table rk3228_cpuclk_rates[] __initdata = {
^
>> drivers/clk/rockchip/clk-rk3228.c:158:34: warning: 'rk3228_pll_clks' defined but not used [-Wunused-variable]
static struct rockchip_pll_clock rk3228_pll_clks[] __initdata = {
^
>> drivers/clk/rockchip/clk-rk3228.c:173:35: warning: 'rk3228_clk_branches' defined but not used [-Wunused-variable]
static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
^
vim +/COMPOSITE_FRAC +667 drivers/clk/rockchip/clk-rk3228.c
307a2e9ac Jeffy Chen 2015-12-11 661 ROCKCHIP_SOFTRST_HIWORD_MASK);
307a2e9ac Jeffy Chen 2015-12-11 662
ef1d9feec Xing Zheng 2016-03-09 663 rockchip_register_restart_notifier(ctx, RK3228_GLB_SRST_FST, NULL);
ef1d9feec Xing Zheng 2016-03-09 664
ef1d9feec Xing Zheng 2016-03-09 665 rockchip_clk_of_add_provider(np, ctx);
307a2e9ac Jeffy Chen 2015-12-11 666 }
307a2e9ac Jeffy Chen 2015-12-11 @667 CLK_OF_DECLARE(rk3228_cru, "rockchip,rk3228-cru", rk3228_clk_init);
:::::: The code at line 667 was first introduced by commit
:::::: 307a2e9ac524bbec707c0e2b47ca50adaecc23f2 clk: rockchip: add clock controller for rk3228
:::::: TO: Jeffy Chen <jeffy.chen@rock-chips.com>
:::::: CC: Heiko Stuebner <heiko@sntech.de>
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c index 016bdb0..2f1442f 100644 --- a/drivers/clk/rockchip/clk-rk3228.c +++ b/drivers/clk/rockchip/clk-rk3228.c @@ -335,7 +335,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = { RK2928_CLKGATE_CON(2), 6, GFLAGS), GATE(0, "sclk_hsadc", "ext_hsadc", 0, - RK3288_CLKGATE_CON(10), 12, GFLAGS), + RK2928_CLKGATE_CON(10), 12, GFLAGS), COMPOSITE(0, "sclk_wifi", mux_pll_src_cpll_gpll_usb480m_p, 0, RK2928_CLKSEL_CON(23), 5, 2, MFLAGS, 0, 6, DFLAGS, @@ -380,8 +380,8 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = { RK2928_CLKSEL_CON(9), 15, 1, MFLAGS, 0, 7, DFLAGS, RK2928_CLKGATE_CON(0), 3, GFLAGS), COMPOSITE_FRAC(0, "i2s0_frac", "i2s0_src", CLK_SET_RATE_PARENT, - RK3288_CLKSEL_CON(8), 0, - RK3288_CLKGATE_CON(0), 4, GFLAGS), + RK2928_CLKSEL_CON(8), 0, + RK2928_CLKGATE_CON(0), 4, GFLAGS), COMPOSITE_NODIV(SCLK_I2S0, "sclk_i2s0", mux_i2s0_p, 0, RK2928_CLKSEL_CON(9), 8, 2, MFLAGS, RK2928_CLKGATE_CON(0), 5, GFLAGS), @@ -390,8 +390,8 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = { RK2928_CLKSEL_CON(3), 15, 1, MFLAGS, 0, 7, DFLAGS, RK2928_CLKGATE_CON(0), 10, GFLAGS), COMPOSITE_FRAC(0, "i2s1_frac", "i2s1_src", CLK_SET_RATE_PARENT, - RK3288_CLKSEL_CON(7), 0, - RK3288_CLKGATE_CON(0), 11, GFLAGS), + RK2928_CLKSEL_CON(7), 0, + RK2928_CLKGATE_CON(0), 11, GFLAGS, MUX(0, "i2s1_pre", mux_i2s1_pre_p, 0, RK2928_CLKSEL_CON(3), 8, 2, MFLAGS), GATE(SCLK_I2S1, "sclk_i2s1", "i2s1_pre", 0, @@ -404,8 +404,8 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = { RK2928_CLKSEL_CON(16), 15, 1, MFLAGS, 0, 7, DFLAGS, RK2928_CLKGATE_CON(0), 7, GFLAGS), COMPOSITE_FRAC(0, "i2s2_frac", "i2s2_src", CLK_SET_RATE_PARENT, - RK3288_CLKSEL_CON(30), 0, - RK3288_CLKGATE_CON(0), 8, GFLAGS), + RK2928_CLKSEL_CON(30), 0, + RK2928_CLKGATE_CON(0), 8, GFLAGS), COMPOSITE_NODIV(SCLK_I2S2, "sclk_i2s2", mux_i2s2_p, 0, RK2928_CLKSEL_CON(16), 8, 2, MFLAGS, RK2928_CLKGATE_CON(0), 9, GFLAGS), @@ -414,8 +414,8 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = { RK2928_CLKSEL_CON(6), 15, 1, MFLAGS, 0, 7, DFLAGS, RK2928_CLKGATE_CON(2), 10, GFLAGS), COMPOSITE_FRAC(0, "spdif_frac", "sclk_spdif_src", CLK_SET_RATE_PARENT, - RK3288_CLKSEL_CON(20), 0, - RK3288_CLKGATE_CON(2), 12, GFLAGS), + RK2928_CLKSEL_CON(20), 0, + RK2928_CLKGATE_CON(2), 12, GFLAGS), MUX(SCLK_SPDIF, "sclk_spdif", mux_sclk_spdif_p, 0, RK2928_CLKSEL_CON(6), 8, 2, MFLAGS),
Due to copy and paste carelessly, RK3288_CLKxxx nodes are incorrect, we need to fix them. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> --- drivers/clk/rockchip/clk-rk3228.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-)