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[92.17.247.99]) by smtp.gmail.com with ESMTPSA id bf5sm11829355wjc.12.2016.06.21.10.24.41 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 21 Jun 2016 10:24:42 -0700 (PDT) From: Srinivas Kandagatla To: Andy Gross Subject: [PATCH v2 2/8] arm64: dts: db820c: add support to LS-UART0 Date: Tue, 21 Jun 2016 18:22:43 +0100 Message-Id: <1466529769-2674-3-git-send-email-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1466529769-2674-1-git-send-email-srinivas.kandagatla@linaro.org> References: <1466529769-2674-1-git-send-email-srinivas.kandagatla@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160621_102505_231054_F4034228 X-CRM114-Status: GOOD ( 11.19 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, David Brown , Rob Herring , Srinivas Kandagatla , linux-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds support to 4 pin UART0 on LS expansion connector. Signed-off-by: Srinivas Kandagatla --- arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi index 01916a5..2851442 100644 --- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi +++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi @@ -16,6 +16,7 @@ / { aliases { serial0 = &blsp2_uart1; + serial1 = &blsp2_uart2; }; chosen { @@ -30,5 +31,13 @@ pinctrl-0 = <&blsp2_uart1_2pins_default>; pinctrl-1 = <&blsp2_uart1_2pins_sleep>; }; + + serial@75b1000 { + label = "LS-UART0"; + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp2_uart2_4pins_default>; + pinctrl-1 = <&blsp2_uart2_4pins_sleep>; + }; }; };