From patchwork Mon Jun 27 21:54:16 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tai Nguyen X-Patchwork-Id: 9201483 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id DFF2360757 for ; Mon, 27 Jun 2016 21:59:42 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CFEA5285B6 for ; Mon, 27 Jun 2016 21:59:42 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C47B9285C5; Mon, 27 Jun 2016 21:59:42 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED, T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 7B0CD285B6 for ; Mon, 27 Jun 2016 21:59:42 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.85_2 #1 (Red Hat Linux)) id 1bHeXP-0002pG-4s; Mon, 27 Jun 2016 21:57:51 +0000 Received: from mail-pf0-x22d.google.com ([2607:f8b0:400e:c00::22d]) by bombadil.infradead.org with esmtps (Exim 4.85_2 #1 (Red Hat Linux)) id 1bHeX7-0002lw-TN for linux-arm-kernel@lists.infradead.org; Mon, 27 Jun 2016 21:57:35 +0000 Received: by mail-pf0-x22d.google.com with SMTP id t190so65657395pfb.3 for ; Mon, 27 Jun 2016 14:57:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=apm.com; s=apm; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=1JeXyp54SZ8UUKVP3jw3VyFPdhn0yR+m+Z8MgA6OEZg=; b=XVhMj9fVH6bKCxvS2rdlinNCl+hS00XlcnG24GS1hKmS+QrPlwdz1dqiqpTtDb0njf e+jY0iiKRNQEPa5qNRRsDcQ32XjKwJ1YJW1M5NqJmgLMC//xWrEGoRyPZclJG2NFN9WQ KJYOCclPtxC7Treep9m4JbFWaRJTG6Opxocr4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=1JeXyp54SZ8UUKVP3jw3VyFPdhn0yR+m+Z8MgA6OEZg=; b=OPjEaW06fwdhZmAjd8wRPo8xe9jk5JQ6Pl44p5O2sLXIbS2CJTl74R35SUnh7f7Pbk Qq8nurHIx7fmvPkqcweYaBS0ffx3MsUpt99L2KgmnaoWbmFzlnrNRrpU/H6QgmdJwkhW 9QEolN/Hu3XAVAO7xQRqcrZzykXT3i5sd13mq7fHH4yj1OsVS0BOs8y/PUfPv6b0aEH9 /ZhPOZEJLQPYTuKVGLa/8SKFV4Ej7a8IjF/D+w2NG550rBYT/evTeIvScDi4dbem7lSE xQz1BXetAedu8E+7392y4nMQI0+RlANGpBMnaOxZ1pYwYLjiGhVnpo8JhN2+doWWMoFD 2yAQ== X-Gm-Message-State: ALyK8tKvQBDOy2IZ+jAhWpDQqsZanTWca/SRxOszt/bTawNSmTg2L3CaoWEniVzvYXIp/SLf X-Received: by 10.98.22.198 with SMTP id 189mr37645694pfw.74.1467064633102; Mon, 27 Jun 2016 14:57:13 -0700 (PDT) Received: from ttnguyen-Ubuntu.amcc.com ([206.80.4.98]) by smtp.gmail.com with ESMTPSA id c2sm1804112paw.45.2016.06.27.14.57.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 27 Jun 2016 14:57:12 -0700 (PDT) From: Tai Nguyen To: mark.rutland@arm.com, will.deacon@arm.com, catalin.marinas@arm.com Subject: [PATCH v5 2/4] Documentation: Add documentation for APM X-Gene SoC PMU DTS binding Date: Mon, 27 Jun 2016 14:54:16 -0700 Message-Id: <1467064458-22143-3-git-send-email-ttnguyen@apm.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1467064458-22143-1-git-send-email-ttnguyen@apm.com> References: <1467064458-22143-1-git-send-email-ttnguyen@apm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160627_145734_067659_A91964A0 X-CRM114-Status: GOOD ( 13.09 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, patches@apm.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Tai Nguyen MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Tai Nguyen Acked-by: Rob Herring --- .../devicetree/bindings/perf/apm-xgene-pmu.txt | 112 +++++++++++++++++++++ 1 file changed, 112 insertions(+) create mode 100644 Documentation/devicetree/bindings/perf/apm-xgene-pmu.txt diff --git a/Documentation/devicetree/bindings/perf/apm-xgene-pmu.txt b/Documentation/devicetree/bindings/perf/apm-xgene-pmu.txt new file mode 100644 index 0000000..afb11cf --- /dev/null +++ b/Documentation/devicetree/bindings/perf/apm-xgene-pmu.txt @@ -0,0 +1,112 @@ +* APM X-Gene SoC PMU bindings + +This is APM X-Gene SoC PMU (Performance Monitoring Unit) module. +The following PMU devices are supported: + + L3C - L3 cache controller + IOB - IO bridge + MCB - Memory controller bridge + MC - Memory controller + +The following section describes the SoC PMU DT node binding. + +Required properties: +- compatible : Shall be "apm,xgene-pmu" for revision 1 or + "apm,xgene-pmu-v2" for revision 2. +- regmap-csw : Regmap of the CPU switch fabric (CSW) resource. +- regmap-mcba : Regmap of the MCB-A (memory bridge) resource. +- regmap-mcbb : Regmap of the MCB-B (memory bridge) resource. +- reg : First resource shall be the CPU bus PMU resource. +- interrupts : Interrupt-specifier for PMU IRQ. + +Required properties for L3C subnode: +- compatible : Shall be "apm,xgene-pmu-l3c". +- reg : First resource shall be the L3C PMU resource. + +Required properties for IOB subnode: +- compatible : Shall be "apm,xgene-pmu-iob". +- reg : First resource shall be the IOB PMU resource. + +Required properties for MCB subnode: +- compatible : Shall be "apm,xgene-pmu-mcb". +- reg : First resource shall be the MCB PMU resource. +- enable-bit-index : The bit indicates if the according MCB is enabled. + +Required properties for MC subnode: +- compatible : Shall be "apm,xgene-pmu-mc". +- reg : First resource shall be the MC PMU resource. +- enable-bit-index : The bit indicates if the according MC is enabled. + +Example: + csw: csw@7e200000 { + compatible = "apm,xgene-csw", "syscon"; + reg = <0x0 0x7e200000 0x0 0x1000>; + }; + + mcba: mcba@7e700000 { + compatible = "apm,xgene-mcb", "syscon"; + reg = <0x0 0x7e700000 0x0 0x1000>; + }; + + mcbb: mcbb@7e720000 { + compatible = "apm,xgene-mcb", "syscon"; + reg = <0x0 0x7e720000 0x0 0x1000>; + }; + + pmu: pmu@78810000 { + compatible = "apm,xgene-pmu-v2"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + regmap-csw = <&csw>; + regmap-mcba = <&mcba>; + regmap-mcbb = <&mcbb>; + reg = <0x0 0x78810000 0x0 0x1000>; + interrupts = <0x0 0x22 0x4>; + + pmul3c@7e610000 { + compatible = "apm,xgene-pmu-l3c"; + reg = <0x0 0x7e610000 0x0 0x1000>; + }; + + pmuiob@7e940000 { + compatible = "apm,xgene-pmu-iob"; + reg = <0x0 0x7e940000 0x0 0x1000>; + }; + + pmucmcb@7e710000 { + compatible = "apm,xgene-pmu-mcb"; + reg = <0x0 0x7e710000 0x0 0x1000>; + enable-bit-index = <0>; + }; + + pmucmcb@7e730000 { + compatible = "apm,xgene-pmu-mcb"; + reg = <0x0 0x7e730000 0x0 0x1000>; + enable-bit-index = <1>; + }; + + pmucmc@7e810000 { + compatible = "apm,xgene-pmu-mc"; + reg = <0x0 0x7e810000 0x0 0x1000>; + enable-bit-index = <0>; + }; + + pmucmc@7e850000 { + compatible = "apm,xgene-pmu-mc"; + reg = <0x0 0x7e850000 0x0 0x1000>; + enable-bit-index = <1>; + }; + + pmucmc@7e890000 { + compatible = "apm,xgene-pmu-mc"; + reg = <0x0 0x7e890000 0x0 0x1000>; + enable-bit-index = <2>; + }; + + pmucmc@7e8d0000 { + compatible = "apm,xgene-pmu-mc"; + reg = <0x0 0x7e8d0000 0x0 0x1000>; + enable-bit-index = <3>; + }; + };