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[2.238.57.164]) by smtp.gmail.com with ESMTPSA id k3sm3512653wju.29.2016.06.29.05.35.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 29 Jun 2016 05:35:37 -0700 (PDT) From: Carlo Caione To: linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux@endlessm.com, devicetree@vger.kernel.org, khilman@baylibre.com, mark.rutland@arm.com, robh+dt@kernel.org, matthias.bgg@gmail.com, narmstrong@baylibre.com, bjdooks@googlemail.com, srinivas.kandagatla@linaro.org, maxime.ripard@free-electrons.com Subject: [PATCH v2 6/6] ARM64: dts: amlogic: gxbb: Enable NVMEM Date: Wed, 29 Jun 2016 14:34:16 +0200 Message-Id: <1467203656-14381-7-git-send-email-carlo@caione.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1467203656-14381-1-git-send-email-carlo@caione.org> References: <1467203656-14381-1-git-send-email-carlo@caione.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160629_053600_135117_409F8D39 X-CRM114-Status: UNSURE ( 8.53 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Carlo Caione MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Carlo Caione Add the NVMEM device node in the DTSI. Signed-off-by: Carlo Caione --- arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi index f2a4734..f20f990 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi @@ -103,6 +103,24 @@ }; }; + efuse: efuse { + compatible = "amlogic,meson-gxbb-efuse"; + #address-cells = <1>; + #size-cells = <1>; + + sn: sn@14 { + reg = <0x14 0x10>; + }; + + eth_mac: eth_mac@34 { + reg = <0x34 0x10>; + }; + + bid: bid@46 { + reg = <0x46 0x30>; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts =