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Thu, 7 Jul 2016 00:24:19 -0700 (MST) Received: from samsunx.samsung ([10.113.63.54]) by mmp1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0O9X008W4OKG1C40@mmp1.samsung.com>; Thu, 07 Jul 2016 16:24:19 +0900 (KST) From: Andi Shyti To: Mark Brown Subject: [PATCH] spi: s3c64xx: do not disable the clock while configuring the spi Date: Thu, 07 Jul 2016 16:23:57 +0900 Message-id: <1467876237-12183-1-git-send-email-andi.shyti@samsung.com> X-Mailer: git-send-email 2.8.1 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrALMWRmVeSWpSXmKPExsWyRsSkQHcxc124wcJV6hbbjzxjtVj84zmT xdSHT9gsXr8wtOh//JrZYtPja6wWl3fNYbOYcX4fk0Xjx5vsFofftLM6cHlcX/KJ2WPTqk42 j81L6j36tqxi9Pi8SS6ANYrLJiU1J7MstUjfLoErY8eR9awFf/kqjq2JaWCcy9PFyMkhIWAi 8Xz1E1YIW0ziwr31bF2MXBxCAisYJX5d2MUCU7R1515WiMRSRol/fxuZQBJCAh8ZJY5sqgax 2QQ0JZpu/2ADsUUElCWuft/LAtLALHCaSWLZ+TfMIAlhgWCJ9S0PGEFsFgFViXVHdoGt5hVw k/i19BE7xDY5icvTH4CdISEwj11i4rFJTBANAhLfJh8CmsoBlJCV2HSAGaJeUuLgihssExgF FzAyrGIUTS1ILihOSi8y1itOzC0uzUvXS87P3cQIDOjT/57172C8e8D6EKMAB6MSD++Gqtpw IdbEsuLK3EOMpkAbJjJLiSbnA+MmryTe0NjMyMLUxNTYyNzSTEmcd6HUz2AhgfTEktTs1NSC 1KL4otKc1OJDjEwcnFINjFtYtZnMCwLOZj5Zw1tam9lz9mjLk9Tndfc3iOwRWJB/N3qbH+vC mvSzLrwLBBbMC9/LU9W6uPICS0Oaxou7e27eqLC47G/QZ7XIPH55f90GnhVXSzisWl/Euwvb /zyiz3dpe/xdJ8tS4fn667kVDj5ObXhgbnJnwv0Di9IuHL6a+u2ZxAGbXiWW4oxEQy3mouJE ANvQqopjAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprLIsWRmVeSWpSXmKPExsVy+t9jAd3FzHXhBsv3K1psP/KM1WLxj+dM FlMfPmGzeP3C0KL/8Wtmi02Pr7FaXN41h81ixvl9TBaNH2+yWxx+087qwOVxfcknZo9NqzrZ PDYvqffo27KK0ePzJrkA1qgGRpuM1MSU1CKF1Lzk/JTMvHRbJe/geOd4UzMDQ11DSwtzJYW8 xNxUWyUXnwBdt8wcoKOUFMoSc0qBQgGJxcVK+naYJoSGuOlawDRG6PqGBMH1GBmggYQ1jBk7 jqxnLfjLV3FsTUwD41yeLkZODgkBE4mtO/eyQthiEhfurWfrYuTiEBJYyijx728jE0hCSOAj o8SRTdUgNpuApkTT7R9sILaIgLLE1e97WUAamAVOM0ksO/+GGSQhLBAssb7lASOIzSKgKrHu yC6wDbwCbhK/lj5ih9gmJ3F5+gO2CYzcCxgZVjFKpBYkFxQnpeca5aWW6xUn5haX5qXrJefn bmIER80z6R2Mh3e5H2IU4GBU4uFdkFMbLsSaWFZcmXuIUYKDWUmEd+NfoBBvSmJlVWpRfnxR aU5q8SFGU6ADJjJLiSbnAyM6ryTe0NjEzMjSyNzQwsjYXEmc9/H/dWFCAumJJanZqakFqUUw fUwcnFINjMpvcxaIdd6OemC8YeMlxiifFHuNjh4DsSVxch+qzE+qvLz9rXedjO/BR89/Jx2e 7Cg896369OVPbs1IUBDOjggKuMv2lfs068ypJ3aleioapLzi+vXQzLUzJVPtWGbjwj8nv2Rw i3x7eCdt86Xeps3flPXmXVp0zfY1W/oRzVNtTza5/NLQX6bEUpyRaKjFXFScCAD0lvN7sAIA AA== DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160707_002443_206554_7BFAAA61 X-CRM114-Status: GOOD ( 13.78 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Krzysztof Kozlowski , linux-samsung-soc@vger.kernel.org, Andi Shyti , linux-kernel@vger.kernel.org, Andi Shyti , linux-spi@vger.kernel.org, Kukjin Kim , Sylwester Nawrocki , linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP When the clock is coming from the cmu it is not required to be disabled and then re-enabled in order to change the rate. Besides, some exynos chipsets (e.g. exynos5433) do not deliver any to the SFR if one from the pclk ("spi" in this case) or sclk ("busclk") is disabled. Remove the clock disabling/enabling to avoid falling into this situation. Signed-off-by: Sylwester Nawrocki Signed-off-by: Andi Shyti Reviewed-by: Krzysztof Kozlowski --- Hi, This patch has been tested by me and Sylwester on Trats2 (exynos4412) and tm2(e) (exynos5433) boards, for big data (which use dma transfer) and small data. It also fixes in exynos5433 a synchronus abort caused by the fact that the pclk (spi) doesn't get delivered if the sclk is disabled (busclk) Thanks, Andi drivers/spi/spi-s3c64xx.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 048c900..c719e73 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -577,9 +577,7 @@ static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd) u32 val; /* Disable Clock */ - if (sdd->port_conf->clk_from_cmu) { - clk_disable_unprepare(sdd->src_clk); - } else { + if (!sdd->port_conf->clk_from_cmu) { val = readl(regs + S3C64XX_SPI_CLK_CFG); val &= ~S3C64XX_SPI_ENCLK_ENABLE; writel(val, regs + S3C64XX_SPI_CLK_CFG); @@ -622,11 +620,7 @@ static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd) writel(val, regs + S3C64XX_SPI_MODE_CFG); if (sdd->port_conf->clk_from_cmu) { - /* Configure Clock */ - /* There is half-multiplier before the SPI */ clk_set_rate(sdd->src_clk, sdd->cur_speed * 2); - /* Enable Clock */ - clk_prepare_enable(sdd->src_clk); } else { /* Configure Clock */ val = readl(regs + S3C64XX_SPI_CLK_CFG);