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Thu, 7 Jul 2016 05:14:02 -0700 (MST) Received: from samsunx.samsung ([10.113.63.54]) by mmp2.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0O9Y00KNF1ZB4D90@mmp2.samsung.com>; Thu, 07 Jul 2016 21:14:02 +0900 (KST) From: Andi Shyti To: Chanwoo Choi Subject: [PATCH v4 2/2] clk: exynos5433: enable sclk_ioclk for SPI3 Date: Thu, 07 Jul 2016 21:13:57 +0900 Message-id: <1467893637-12573-3-git-send-email-andi.shyti@samsung.com> X-Mailer: git-send-email 2.8.1 In-reply-to: <1467893637-12573-1-git-send-email-andi.shyti@samsung.com> References: <1467893637-12573-1-git-send-email-andi.shyti@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupgkeLIzCtJLcpLzFFi42JZI2JSqNvlXhdusGqNjsX2I89YLRb/eM5k cf3Lc1aLG7/aWC1evzC06H/8mtli0+NrrBYfe+6xWlzeNYfNYsb5fUwWF0+5Whx+085q8eNM N4vFql1/GB34PN7faGX3uNzXy+RxfcknZo+ds+6ye2xa1cnmsXlJvUffllWMHp83yQVwRHHZ pKTmZJalFunbJXBl9C/gKdjNVdHycCdLA2MrZxcjJ4eEgInE/xMnmSBsMYkL99azdTFycQgJ rGCU2D1hNRNM0YSLCxghErMYJWYs2sAK4XxklHh38S0zSBWbgKZE0+0fbCC2iICGxMy/VxhB bGaBT8wSH/t8QGxhAWeJpmlbgJo5OFgEVCUW7uUBCfMKuEn0T1/ECLFMTuLy9AdgYzgF3CWO rPsENl4IpObHIWaImnvsEp2rEkFsFgEBiW+TD7GAjJQQkJXYdACqRFLi4IobLBMYhRcwMqxi FE0tSC4oTkovMtQrTswtLs1L10vOz93ECIyg0/+e9e5gvH3A+hCjAAejEg/vgY7acCHWxLLi ytxDjKZAGyYyS4km5wPjNK8k3tDYzMjC1MTU2Mjc0kxJnFdR6mewkEB6YklqdmpqQWpRfFFp TmrxIUYmDk6pBsb81Ef77/JteVK2wFzm+6tDBYv8Wtj91cSfR60OuDuXq2Iia1lKURRrQtes MC+3Sf/9nO4vq+1eFqz3vmG3oLxjW2nUminPxBiXnmHjf7ra5FfC96cdp5/b7XZP/lF6//jL 7WzfDC8+e8Pz2eOGudqibu3pd3euT5i4tWa9k/PO9xY3UxpEP0kpsRRnJBpqMRcVJwIADRW9 TpsCAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrGIsWRmVeSWpSXmKPExsVy+t9jQd0u97pwg/n/1Cy2H3nGarH4x3Mm i+tfnrNa3PjVxmrx+oWhRf/j18wWmx5fY7X42HOP1eLyrjlsFjPO72OyuHjK1eLwm3ZWix9n ulksVu36w+jA5/H+Riu7x+W+XiaP60s+MXvsnHWX3WPTqk42j81L6j36tqxi9Pi8SS6AI6qB 0SYjNTEltUghNS85PyUzL91WyTs43jne1MzAUNfQ0sJcSSEvMTfVVsnFJ0DXLTMH6GwlhbLE nFKgUEBicbGSvh2mCaEhbroWMI0Rur4hQXA9RgZoIGENY0b/Ap6C3VwVLQ93sjQwtnJ2MXJy SAiYSEy4uIARwhaTuHBvPVsXIxeHkMAsRokZizawQjgfGSXeXXzLDFLFJqAp0XT7BxuILSKg ITHz7xWwbmaBT8wSH/t8QGxhAWeJpmlbgJo5OFgEVCUW7uUBCfMKuEn0T18EtUxO4vL0B2Bj OAXcJY6s+wQ2Xgik5sch5gmMvAsYGVYxSqQWJBcUJ6XnGuWllusVJ+YWl+al6yXn525iBMfp M+kdjId3uR9iFOBgVOLhXZBTGy7EmlhWXJl7iFGCg1lJhNfDpS5ciDclsbIqtSg/vqg0J7X4 EKMp0F0TmaVEk/OBKSSvJN7Q2MTMyNLI3NDCyNhcSZz38f91YUIC6YklqdmpqQWpRTB9TByc Ug2MMbEfzF+aO503lNqTUP7mXt/085x/TF+7XVi/mWPzDmveOzrC7fNC6jordhh3XZ/k7ios 0h8dbXA8ZvIv/sm+Tj3S+4wT+Hm7NCobz6/7E6uqLqDon3NIm2/ed71D16w+fHIXDGxYU6nv dNDlHO+N9pOpXXq3AjwPGp/0Dvy39v4hh6NR50qUWIozEg21mIuKEwE/vus/6QIAAA== DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160707_051425_097426_63D6BD0B X-CRM114-Status: GOOD ( 12.19 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Krzysztof Kozlowski , linux-samsung-soc@vger.kernel.org, Andi Shyti , Michael Turquette , Stephen Boyd , Tomasz Figa , Andi Shyti , linux-kernel@vger.kernel.org, Jaehoon Chung , Kukjin Kim , Sylwester Nawrocki , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP enable SPI3 critical clocks by using the CLK_IS_CRITICAL flag. There is no device which is supposed to enable this clock when needed, therefore, the only way to use the SPI bus is to enable it in boot time. Suggested-by: Tomasz Figa Signed-off-by: Andi Shyti Signed-off-by: Jaehoon Chung Reviewed-by: Chanwoo Choi --- drivers/clk/samsung/clk-exynos5433.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c index 337387b..fb8d330 100644 --- a/drivers/clk/samsung/clk-exynos5433.c +++ b/drivers/clk/samsung/clk-exynos5433.c @@ -1648,7 +1648,8 @@ static struct samsung_gate_clock peric_gate_clks[] __initdata = { GATE(CLK_SCLK_IOCLK_SPI4, "sclk_ioclk_spi4", "ioclk_spi4_clk_in", ENABLE_SCLK_PERIC, 21, CLK_SET_RATE_PARENT, 0), GATE(CLK_SCLK_IOCLK_SPI3, "sclk_ioclk_spi3", "ioclk_spi3_clk_in", - ENABLE_SCLK_PERIC, 20, CLK_SET_RATE_PARENT, 0), + ENABLE_SCLK_PERIC, 20, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), GATE(CLK_SCLK_SPI4, "sclk_spi4", "sclk_spi4_peric", ENABLE_SCLK_PERIC, 19, CLK_SET_RATE_PARENT, 0), GATE(CLK_SCLK_SPI3, "sclk_spi3", "sclk_spi3_peric", ENABLE_SCLK_PERIC,