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[06/15] net: thunderx: Enable mailbox interrupts on 81xx/83xx

Message ID 1468231317-24023-7-git-send-email-sunil.kovvuri@gmail.com (mailing list archive)
State New, archived
Headers show

Commit Message

Sunil Kovvuri July 11, 2016, 10:01 a.m. UTC 
From: Sunil Goutham <sgoutham@cavium.com>

88xx has 128 VFs, 81xx has 8 VFs and 83xx will have 32VFs.
Made changes to PF driver such that mailbox interrupt enable
registers are configuired based on number of VFs HW supports.
Also cleanedup mailbox irq handler registration code.

Signed-off-by: Sunil Goutham <sgoutham@cavium.com>
---
 drivers/net/ethernet/cavium/thunder/nic_main.c | 77 +++++++++++++-------------
 1 file changed, 40 insertions(+), 37 deletions(-)

Comments

kernel test robot July 11, 2016, 11:41 a.m. UTC | #1 
Hi,

[auto build test WARNING on net-next/master]
[also build test WARNING on v4.7-rc7 next-20160711]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/sunil-kovvuri-gmail-com/net-thunderx-Add-support-for-81xx-and-83xx/20160711-181138
config: x86_64-randconfig-i0-201628 (attached as .config)
compiler: gcc-6 (Debian 6.1.1-1) 6.1.1 20160430
reproduce:
        # save the attached .config to linux build tree
        make ARCH=x86_64 

All warnings (new ones prefixed by >>):

   drivers/net/ethernet/cavium/thunder/nic_main.c: In function 'nic_enable_msix':
>> drivers/net/ethernet/cavium/thunder/nic_main.c:944:30: warning: iteration 10 invokes undefined behavior [-Waggressive-loop-optimizations]
      nic->msix_entries[i].entry = i;
      ~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~
   drivers/net/ethernet/cavium/thunder/nic_main.c:943:2: note: within this loop
     for (i = 0; i < nic->num_vec; i++)
     ^~~

vim +944 drivers/net/ethernet/cavium/thunder/nic_main.c

4863dea3 Sunil Goutham 2015-05-26  928  				vf + (mbx * vf_per_mbx_reg));
92dc8769 Sunil Goutham 2015-08-30  929  
4863dea3 Sunil Goutham 2015-05-26  930  			nic_handle_mbx_intr(nic, vf + (mbx * vf_per_mbx_reg));
4863dea3 Sunil Goutham 2015-05-26  931  			nic_clear_mbx_intr(nic, vf, mbx);
4863dea3 Sunil Goutham 2015-05-26  932  		}
4863dea3 Sunil Goutham 2015-05-26  933  	}
4863dea3 Sunil Goutham 2015-05-26  934  	return IRQ_HANDLED;
4863dea3 Sunil Goutham 2015-05-26  935  }
4863dea3 Sunil Goutham 2015-05-26  936  
4863dea3 Sunil Goutham 2015-05-26  937  static int nic_enable_msix(struct nicpf *nic)
4863dea3 Sunil Goutham 2015-05-26  938  {
4863dea3 Sunil Goutham 2015-05-26  939  	int i, ret;
4863dea3 Sunil Goutham 2015-05-26  940  
45ff737f Sunil Goutham 2016-07-11  941  	nic->num_vec = pci_msix_vec_count(nic->pdev);
4863dea3 Sunil Goutham 2015-05-26  942  
4863dea3 Sunil Goutham 2015-05-26  943  	for (i = 0; i < nic->num_vec; i++)
4863dea3 Sunil Goutham 2015-05-26 @944  		nic->msix_entries[i].entry = i;
4863dea3 Sunil Goutham 2015-05-26  945  
4863dea3 Sunil Goutham 2015-05-26  946  	ret = pci_enable_msix(nic->pdev, nic->msix_entries, nic->num_vec);
4863dea3 Sunil Goutham 2015-05-26  947  	if (ret) {
4863dea3 Sunil Goutham 2015-05-26  948  		dev_err(&nic->pdev->dev,
45ff737f Sunil Goutham 2016-07-11  949  			"Request for #%d msix vectors failed, returned %d\n",
45ff737f Sunil Goutham 2016-07-11  950  			   nic->num_vec, ret);
4863dea3 Sunil Goutham 2015-05-26  951  		return ret;
4863dea3 Sunil Goutham 2015-05-26  952  	}

:::::: The code at line 944 was first introduced by commit
:::::: 4863dea3fab01734768c9f7fc2c1590a8f1f6266 net: Adding support for Cavium ThunderX network controller

:::::: TO: Sunil Goutham <sgoutham@cavium.com>
:::::: CC: David S. Miller <davem@davemloft.net>

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation
diff mbox

Patch

diff --git a/drivers/net/ethernet/cavium/thunder/nic_main.c b/drivers/net/ethernet/cavium/thunder/nic_main.c
index 3f52b36..eade508 100644
--- a/drivers/net/ethernet/cavium/thunder/nic_main.c
+++ b/drivers/net/ethernet/cavium/thunder/nic_main.c
@@ -68,6 +68,7 @@  struct nicpf {
 	u8			num_vec;
 	struct msix_entry	msix_entries[NIC_PF_MSIX_VECTORS];
 	bool			irq_allocated[NIC_PF_MSIX_VECTORS];
+	char			irq_name[NIC_PF_MSIX_VECTORS][20];
 };
 
 /* Supported devices */
@@ -105,9 +106,22 @@  static u64 nic_reg_read(struct nicpf *nic, u64 offset)
 /* PF -> VF mailbox communication APIs */
 static void nic_enable_mbx_intr(struct nicpf *nic)
 {
-	/* Enable mailbox interrupt for all 128 VFs */
-	nic_reg_write(nic, NIC_PF_MAILBOX_ENA_W1S, ~0ull);
-	nic_reg_write(nic, NIC_PF_MAILBOX_ENA_W1S + sizeof(u64), ~0ull);
+	int vf_cnt = pci_sriov_get_totalvfs(nic->pdev);
+
+#define INTR_MASK(vfs) ((vfs < 64) ? (BIT_ULL(vfs) - 1) : (~0ull))
+
+	/* Clear it, to avoid spurious interrupts (if any) */
+	nic_reg_write(nic, NIC_PF_MAILBOX_INT, INTR_MASK(vf_cnt));
+
+	/* Enable mailbox interrupt for all VFs */
+	nic_reg_write(nic, NIC_PF_MAILBOX_ENA_W1S, INTR_MASK(vf_cnt));
+	/* One mailbox intr enable reg per 64 VFs */
+	if (vf_cnt > 64) {
+		nic_reg_write(nic, NIC_PF_MAILBOX_INT + sizeof(u64),
+			      INTR_MASK(vf_cnt - 64));
+		nic_reg_write(nic, NIC_PF_MAILBOX_ENA_W1S + sizeof(u64),
+			      INTR_MASK(vf_cnt - 64));
+	}
 }
 
 static void nic_clear_mbx_intr(struct nicpf *nic, int vf, int mbx_reg)
@@ -894,11 +908,18 @@  unlock:
 	nic->mbx_lock[vf] = false;
 }
 
-static void nic_mbx_intr_handler (struct nicpf *nic, int mbx)
+static irqreturn_t nic_mbx_intr_handler(int irq, void *nic_irq)
 {
+	struct nicpf *nic = (struct nicpf *)nic_irq;
+	int mbx;
 	u64 intr;
 	u8  vf, vf_per_mbx_reg = 64;
 
+	if (irq == nic->msix_entries[NIC_PF_INTR_ID_MBOX0].vector)
+		mbx = 0;
+	else
+		mbx = 1;
+
 	intr = nic_reg_read(nic, NIC_PF_MAILBOX_INT + (mbx << 3));
 	dev_dbg(&nic->pdev->dev, "PF interrupt Mbox%d 0x%llx\n", mbx, intr);
 	for (vf = 0; vf < vf_per_mbx_reg; vf++) {
@@ -910,23 +931,6 @@  static void nic_mbx_intr_handler (struct nicpf *nic, int mbx)
 			nic_clear_mbx_intr(nic, vf, mbx);
 		}
 	}
-}
-
-static irqreturn_t nic_mbx0_intr_handler (int irq, void *nic_irq)
-{
-	struct nicpf *nic = (struct nicpf *)nic_irq;
-
-	nic_mbx_intr_handler(nic, 0);
-
-	return IRQ_HANDLED;
-}
-
-static irqreturn_t nic_mbx1_intr_handler (int irq, void *nic_irq)
-{
-	struct nicpf *nic = (struct nicpf *)nic_irq;
-
-	nic_mbx_intr_handler(nic, 1);
-
 	return IRQ_HANDLED;
 }
 
@@ -934,7 +938,7 @@  static int nic_enable_msix(struct nicpf *nic)
 {
 	int i, ret;
 
-	nic->num_vec = NIC_PF_MSIX_VECTORS;
+	nic->num_vec = pci_msix_vec_count(nic->pdev);
 
 	for (i = 0; i < nic->num_vec; i++)
 		nic->msix_entries[i].entry = i;
@@ -942,8 +946,8 @@  static int nic_enable_msix(struct nicpf *nic)
 	ret = pci_enable_msix(nic->pdev, nic->msix_entries, nic->num_vec);
 	if (ret) {
 		dev_err(&nic->pdev->dev,
-			"Request for #%d msix vectors failed\n",
-			   nic->num_vec);
+			"Request for #%d msix vectors failed, returned %d\n",
+			   nic->num_vec, ret);
 		return ret;
 	}
 
@@ -973,27 +977,26 @@  static void nic_free_all_interrupts(struct nicpf *nic)
 
 static int nic_register_interrupts(struct nicpf *nic)
 {
-	int ret;
+	int i, ret;
 
 	/* Enable MSI-X */
 	ret = nic_enable_msix(nic);
 	if (ret)
 		return ret;
 
-	/* Register mailbox interrupt handlers */
-	ret = request_irq(nic->msix_entries[NIC_PF_INTR_ID_MBOX0].vector,
-			  nic_mbx0_intr_handler, 0, "NIC Mbox0", nic);
-	if (ret)
-		goto fail;
-
-	nic->irq_allocated[NIC_PF_INTR_ID_MBOX0] = true;
+	/* Register mailbox interrupt handler */
+	for (i = NIC_PF_INTR_ID_MBOX0; i < nic->num_vec; i++) {
+		sprintf(nic->irq_name[i],
+			"NICPF Mbox%d", (i - NIC_PF_INTR_ID_MBOX0));
 
-	ret = request_irq(nic->msix_entries[NIC_PF_INTR_ID_MBOX1].vector,
-			  nic_mbx1_intr_handler, 0, "NIC Mbox1", nic);
-	if (ret)
-		goto fail;
+		ret = request_irq(nic->msix_entries[i].vector,
+				  nic_mbx_intr_handler, 0,
+				  nic->irq_name[i], nic);
+		if (ret)
+			goto fail;
 
-	nic->irq_allocated[NIC_PF_INTR_ID_MBOX1] = true;
+		nic->irq_allocated[i] = true;
+	}
 
 	/* Enable mailbox interrupt */
 	nic_enable_mbx_intr(nic);