From patchwork Wed Jul 13 15:42:47 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Graf X-Patchwork-Id: 9227815 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 586B660572 for ; Wed, 13 Jul 2016 15:44:43 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4A6E326AE3 for ; Wed, 13 Jul 2016 15:44:43 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3EF2527165; Wed, 13 Jul 2016 15:44:43 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id D07F226AE3 for ; Wed, 13 Jul 2016 15:44:42 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.85_2 #1 (Red Hat Linux)) id 1bNMJc-00005e-Sp; Wed, 13 Jul 2016 15:43:12 +0000 Received: from mx2.suse.de ([195.135.220.15]) by bombadil.infradead.org with esmtps (Exim 4.85_2 #1 (Red Hat Linux)) id 1bNMJX-0008U0-TA for linux-arm-kernel@lists.infradead.org; Wed, 13 Jul 2016 15:43:09 +0000 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay1.suse.de (charybdis-ext.suse.de [195.135.220.254]) by mx2.suse.de (Postfix) with ESMTP id 39A58ABA6; Wed, 13 Jul 2016 15:42:44 +0000 (UTC) From: Alexander Graf To: linux-arm-kernel@lists.infradead.org Subject: [PATCH] arm64: Add config to limit user space to 47bits Date: Wed, 13 Jul 2016 17:42:47 +0200 Message-Id: <1468424567-15925-1-git-send-email-agraf@suse.de> X-Mailer: git-send-email 1.8.5.6 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160713_084308_259578_2D87B061 X-CRM114-Status: UNSURE ( 8.87 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , mbrugger@suse.com, Ard Biesheuvel , Catalin Marinas , Will Deacon , linux-kernel@vger.kernel.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Some user space applications are known to break with 48 bits virtual address space. As interim step until the world is healed and everyone embraces correct code, this patch allows to only expose 47 bits of virtual address space to user space. Signed-off-by: Alexander Graf --- arch/arm64/Kconfig | 9 +++++++++ arch/arm64/include/asm/memory.h | 4 ++++ 2 files changed, 13 insertions(+) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 5a0a691..9ff5a74 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -538,6 +538,15 @@ config ARM64_VA_BITS default 47 if ARM64_VA_BITS_47 default 48 if ARM64_VA_BITS_48 +config ARM64_USER_VA_BITS_47 + bool "Limit user space to 47 bits address space" + depends on ARM64_VA_BITS_48 + help + Some user space applications are known to break with 48 bits virtual + address space. As interim step until the world is healed and everyone + embraces correct code, this option allows to only expose 47 bits of + virtual address space to user space. If unsure say N here. + config CPU_BIG_ENDIAN bool "Build big-endian kernel" help diff --git a/arch/arm64/include/asm/memory.h b/arch/arm64/include/asm/memory.h index 31b7322..ef268c6 100644 --- a/arch/arm64/include/asm/memory.h +++ b/arch/arm64/include/asm/memory.h @@ -74,7 +74,11 @@ #define PCI_IO_END (VMEMMAP_START - SZ_2M) #define PCI_IO_START (PCI_IO_END - PCI_IO_SIZE) #define FIXADDR_TOP (PCI_IO_START - SZ_2M) +#ifdef CONFIG_ARM64_USER_VA_BITS_47 +#define TASK_SIZE_64 (UL(1) << (VA_BITS - 1)) +#else #define TASK_SIZE_64 (UL(1) << VA_BITS) +#endif #ifdef CONFIG_COMPAT #define TASK_SIZE_32 UL(0x100000000)