| Message ID | 1469629447-544-3-git-send-email-wxt@rock-chips.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 07/27/2016 07:24 AM, Caesar Wang wrote: > SARADC controller needs to be reset before programming it, otherwise > it will not function properly. > > Signed-off-by: Caesar Wang <wxt@rock-chips.com> Reviewed-by: Guenter Roeck <linux@roeck-us.net> > --- > > Changes in v3: > - add Doug's reviewed tag. > Not to this patch ? > Changes in v2: None > > arch/arm64/boot/dts/rockchip/rk3368.dtsi | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi > index d02a9003..4f44d11 100644 > --- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi > +++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi > @@ -270,6 +270,8 @@ > #io-channel-cells = <1>; > clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; > clock-names = "saradc", "apb_pclk"; > + resets = <&cru SRST_SARADC>; > + reset-names = "saradc-apb"; > status = "disabled"; > }; > >
Am Mittwoch, 27. Juli 2016, 22:24:06 CEST schrieb Caesar Wang: > SARADC controller needs to be reset before programming it, otherwise > it will not function properly. > > Signed-off-by: Caesar Wang <wxt@rock-chips.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Cc: <Stable@vger.kernel.org>
On 22/08/16 18:19, Heiko Stuebner wrote: > Am Mittwoch, 27. Juli 2016, 22:24:06 CEST schrieb Caesar Wang: >> SARADC controller needs to be reset before programming it, otherwise >> it will not function properly. >> >> Signed-off-by: Caesar Wang <wxt@rock-chips.com> > > Acked-by: Heiko Stuebner <heiko@sntech.de> > Cc: <Stable@vger.kernel.org> Thanks, Applied to the fixes-togreg branch of iio.git. Jonathan > > -- > To unsubscribe from this list: send the line "unsubscribe linux-iio" in > the body of a message to majordomo@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html >
diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi index d02a9003..4f44d11 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi @@ -270,6 +270,8 @@ #io-channel-cells = <1>; clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; clock-names = "saradc", "apb_pclk"; + resets = <&cru SRST_SARADC>; + reset-names = "saradc-apb"; status = "disabled"; };
SARADC controller needs to be reset before programming it, otherwise it will not function properly. Signed-off-by: Caesar Wang <wxt@rock-chips.com> --- Changes in v3: - add Doug's reviewed tag. Changes in v2: None arch/arm64/boot/dts/rockchip/rk3368.dtsi | 2 ++ 1 file changed, 2 insertions(+)