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[194.187.74.233]) by smtp.gmail.com with ESMTPSA id g29sm2629028lji.45.2016.07.29.02.23.21 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 29 Jul 2016 02:23:21 -0700 (PDT) From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= To: Daniel Lezcano , Thomas Gleixner Subject: [PATCH] clocksource: arm_arch_timer: Support reading clock rate from a driver Date: Fri, 29 Jul 2016 11:23:11 +0200 Message-Id: <1469784191-3998-1-git-send-email-zajec5@gmail.com> X-Mailer: git-send-email 1.8.4.5 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160729_022345_257332_24268EDD X-CRM114-Status: GOOD ( 13.20 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= , "open list:CLOCKSOURCE, CLOCKEVENT DRIVERS" , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Rafał Miłecki On some devices using arch code for reading clock rate doesn't work. So far the only option was to specify clock-frequency in a DT. This works only if a clock frequency doesn't have to be calculated on runtime. On BCM53573 SoC (with Cortex-A7) there is ILP clock that needs its own driver. With this change we can query such clocks by using a standard: clocks = <&foo>; Signed-off-by: Rafał Miłecki --- drivers/clocksource/arm_arch_timer.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c index 5effd30..5ed98a2 100644 --- a/drivers/clocksource/arm_arch_timer.c +++ b/drivers/clocksource/arm_arch_timer.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -405,6 +406,16 @@ arch_timer_detect_rate(void __iomem *cntbase, struct device_node *np) arch_timer_rate = arch_timer_get_cntfrq(); } + /* Get clk rate through clk driver if present */ + if (!arch_timer_rate) { + struct clk *clk = of_clk_get(np, 0); + + if (!IS_ERR(clk)) { + if (!clk_prepare_enable(clk)) + arch_timer_rate = clk_get_rate(clk); + } + } + /* Check the timer frequency. */ if (arch_timer_rate == 0) pr_warn("Architected timer frequency not available\n");