| Message ID | 1470878029-11878-4-git-send-email-finley.xiao@rock-chips.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Am Donnerstag, 11. August 2016, 09:13:48 schrieb Finlye Xiao: > From: Finley Xiao <finley.xiao@rock-chips.com> > > Add a efuse0 node in the device tree for the ARM64 rk3399 SoC. > > Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com> this patch adds a node for a new compatible, so to limit conflicts in the somewhat high-traffic rk3399, I'd like to pick this patch up myself once the others are deemed suitable. Thanks Heiko
Hi, On Wed, Aug 10, 2016 at 6:13 PM, Finlye Xiao <finley.xiao@rock-chips.com> wrote: > From: Finley Xiao <finley.xiao@rock-chips.com> > > Add a efuse0 node in the device tree for the ARM64 rk3399 SoC. > > Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com> > --- > arch/arm64/boot/dts/rockchip/rk3399.dtsi | 29 +++++++++++++++++++++++++++++ > 1 file changed, 29 insertions(+) Oddly this patch seems to have been dropped from v3 and v4 of the series. Seems like we still need it? > diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi > index 4c84229..7f764ca 100644 > --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi > +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi > @@ -899,6 +899,35 @@ > status = "disabled"; > }; > > + efuse0: efuse0@ff690000 { nit: should be efuse0: efuse@ff690000 AKA get rid of the "0" from the node name and just keep it in the alias. > + compatible = "rockchip,rk3399-efuse"; > + reg = <0x0 0xff690000 0x0 0x80>; > + #address-cells = <1>; > + #size-cells = <1>; > + clocks = <&cru PCLK_EFUSE1024NS>; > + clock-names = "pclk_efuse"; > + > + /* Data cells */ > + cpul_leakage: cpul-leakage { > + reg = <0x1a 0x1>; > + }; > + cpub_leakage: cpub-leakage { > + reg = <0x17 0x1>; > + }; > + gpu_leakage: gpu-leakage { > + reg = <0x18 0x1>; > + }; > + center_leakage: center-leakage { > + reg = <0x19 0x1>; > + }; > + logic_leakage: logic-leakage { > + reg = <0x1b 0x1>; > + }; > + wafer_info: wafer-info { > + reg = <0x1c 0x1>; > + }; > + }; Other than that this looks sane to me. -Doug
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 4c84229..7f764ca 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -899,6 +899,35 @@ status = "disabled"; }; + efuse0: efuse0@ff690000 { + compatible = "rockchip,rk3399-efuse"; + reg = <0x0 0xff690000 0x0 0x80>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cru PCLK_EFUSE1024NS>; + clock-names = "pclk_efuse"; + + /* Data cells */ + cpul_leakage: cpul-leakage { + reg = <0x1a 0x1>; + }; + cpub_leakage: cpub-leakage { + reg = <0x17 0x1>; + }; + gpu_leakage: gpu-leakage { + reg = <0x18 0x1>; + }; + center_leakage: center-leakage { + reg = <0x19 0x1>; + }; + logic_leakage: logic-leakage { + reg = <0x1b 0x1>; + }; + wafer_info: wafer-info { + reg = <0x1c 0x1>; + }; + }; + pmucru: pmu-clock-controller@ff750000 { compatible = "rockchip,rk3399-pmucru"; reg = <0x0 0xff750000 0x0 0x1000>;