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Mon, 15 Aug 2016 23:27:46 -0700 (MST) Received: from chan.10.32.193.11 ([10.113.62.212]) by mmp2.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0OBZ003A3OM8Q470@mmp2.samsung.com>; Tue, 16 Aug 2016 15:27:45 +0900 (KST) From: Chanwoo Choi To: k.kozlowski@samsung.com, kgene@kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, catalin.marinas@arm.com, will.deacon@arm.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/7] pinctrl: samsung: Add GPFx support of Exynos5433 Date: Tue, 16 Aug 2016 15:27:20 +0900 Message-id: <1471328843-26653-5-git-send-email-cw00.choi@samsung.com> X-Mailer: git-send-email 1.8.0 In-reply-to: <1471328843-26653-1-git-send-email-cw00.choi@samsung.com> References: <1471328843-26653-1-git-send-email-cw00.choi@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrCIsWRmVeSWpSXmKPExsWyRsSkQDdp06ZwgxU9Iha31p1jtTj9aRu7 xftlPYwWE29cYbG4/uU5q8X8I0CJpTP6WC12/b3PaLHj5hc2i0n3J7BY7Gg4wmpx41cbq0Xn 2SfMFi/uXWSxeP3C0KL/8Wtmi/PnN7BbTPmznMli0+NrrBab5/9htLi8aw6bxYzz+5gs1h65 y26x9PpFJovWvUfYLQ6/aWe1mDH5JZvFql1AdS8/nmBxkPVYM28No8fOWXfZPTat6mTzuHNt D5vH5iX1Hn1bVjF6fN4kF8AexWWTkpqTWZZapG+XwJVxbecb5oKpARXvD/9ibWBc79TFyMkh IWAisWbSVxYIW0ziwr31bF2MXBxCAisYJc7fXcAKU7Tt2QUmiMQsRok3l5+xQzhfGCW+bV7P DFLFJqAlsf/FDbB2EYE+Jollp86CtTALvGeWuLuqgwmkSljAVeJrw2M2EJtFQFXi7IY+RhCb Fyi+btslJoh9chIf9jxiB7E5BdwkfixaDHagEFDNqTPzwFZLCJzhkDj38DYzxCABiW+TDwEV cQAlZCU2HWCGmCMpcXDFDZYJjMILGBlWMYqmFiQXFCelFxnqFSfmFpfmpesl5+duYgRG9ul/ z3p3MN4+YH2IUYCDUYmH12LdpnAh1sSy4srcQ4ymQBsmMkuJJucD00deSbyhsZmRhamJqbGR uaWZkjivotTPYCGB9MSS1OzU1ILUovii0pzU4kOMTBycUg2MLe+rTW7IvNDROzLvy5ulWyf/ /PI/dIFn1axzqttPde4Inf9Vd2OQ0e/Xbw7+3bglqW21asdpjprnE2871qnkOrRsMEywbr28 IvUCa5VpyPmmKVXVFs+d9wU0zuy+OnWGk+PMgGM3HoZKOuS+yBSNu3x8q2TRoq8i39Vf2Vnu l9ZzNJGUFZQ2VmIpzkg01GIuKk4EAFbwFvXnAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrIKsWRmVeSWpSXmKPExsVy+t9jQd2kTZvCDWac57S4te4cq8XpT9vY Ld4v62G0mHjjCovF9S/PWS3mHwFKLJ3Rx2qx6+99RosdN7+wWUy6P4HFYkfDEVaLG7/aWC06 zz5htnhx7yKLxesXhhb9j18zW5w/v4HdYsqf5UwWmx5fY7XYPP8Po8XlXXPYLGac38dksfbI XXaLpdcvMlm07j3CbnH4TTurxYzJL9ksVu0Cqnv58QSLg6zHmnlrGD12zrrL7rFpVSebx51r e9g8Ni+p9+jbsorR4/MmuQD2qAZGm4zUxJTUIoXUvOT8lMy8dFsl7+B453hTMwNDXUNLC3Ml hbzE3FRbJRefAF23zByg75UUyhJzSoFCAYnFxUr6dpgmhIa46VrANEbo+oYEwfUYGaCBhDWM Gdd2vmEumBpQ8f7wL9YGxvVOXYycHBICJhLbnl1ggrDFJC7cW8/WxcjFISQwi1HizeVn7BDO F0aJb5vXM4NUsQloSex/cQOsSkSgj0li2amzTCAOs8B7Zom7qzrAZgkLuEp8bXjMBmKzCKhK nN3Qxwhi8wLF1227BLVPTuLDnkfsIDangJvEj0WLWUBsIaCaU2fmsU9g5F3AyLCKUSK1ILmg OCk91ygvtVyvODG3uDQvXS85P3cTIzh5PJPewXh4l/shRgEORiUe3hMMm8KFWBPLiitzDzFK cDArifC6rAMK8aYkVlalFuXHF5XmpBYfYjQFOmwis5Rocj4wseWVxBsam5gZWRqZG1oYGZsr ifM+/r8uTEggPbEkNTs1tSC1CKaPiYNTqoHR+ptk1d4yzTcp99sXPs25dYNlfaxvZEe0dc63 y0dWLW2wPLHC8/9N2RcvPxisaJr6P+roH8tlDO4c0+OTr/9P+FI3Q8jjr+T6LucTf1OYTNVL bt/ck3HA4dJ5iQ8Rm844hxfu/pRdN0F/Sa9jPEPdiyOfrb7fO6lQ+P/q89TnhnEZryfZu/m7 KrEUZyQaajEXFScCAHuFtlg0AwAA DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160815_232811_604990_DE7F73D2 X-CRM114-Status: GOOD ( 20.88 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: inki.dae@samsung.com, jonghwa3.lee@samsung.com, s.nawrocki@samsung.com, jy0922.shim@samsung.com, a.hajda@samsung.com, jaewon02.kim@samsung.com, Linus Walleij , sw0312.kim@samsung.com, Tomasz Figa , krzk@kernel.org, jh80.chung@samsung.com, cw00.choi@samsung.com, human.hwang@samsung.com, linux-gpio@vger.kernel.org, chanwoo@kernel.org, ingi2.kim@samsung.com, m.szyprowski@samsung.com, beomho.seo@samsung.com, ideal.song@samsung.com MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Joonyoung Shim This patch add the support of GPFx pin of Exynos5433 SoC. Exynos5433 has different memory map of GPFx from previous Exynos SoC. Exynos GPIO has following register to control gpio funciton. Usually, all registers of GPIO are included in same domain. - CON / DAT / PUD / DRV / CONPDN / PUDPDN - EINT_CON/ EINT_FLTCON0, EINT_FLTCON1 / EINT_MASK / EINT_PEND But, GPFx are included in two domain as following. So, this patch supports the GPFx pin which handle the on separate two domains. - ALIVE domain : CON / DAT / PUD / DRV / CONPDN / PUDPDN - IMEM domain : EINT_CON/ EINT_FLTCON0, EINT_FLTCON1 / EINT_MASK / EINT_PEND Cc: Linus Walleij Cc: Rob Herring Cc: Mark Rutland Cc: Tomasz Figa Cc: Krzysztof Kozlowski Cc: Sylwester Nawrocki Cc: Kukjin Kim Cc: linux-gpio@vger.kernel.org Signed-off-by: Joonyoung Shim Signed-off-by: Chanwoo Choi Acked-by: Rob Herring --- .../bindings/pinctrl/samsung-pinctrl.txt | 1 + drivers/pinctrl/samsung/pinctrl-exynos.c | 5 +++ drivers/pinctrl/samsung/pinctrl-exynos.h | 11 ++++++ drivers/pinctrl/samsung/pinctrl-samsung.c | 43 ++++++++++++++++++---- drivers/pinctrl/samsung/pinctrl-samsung.h | 5 +++ 5 files changed, 57 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt index 6db16b90873a..807fba1f829f 100644 --- a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt @@ -19,6 +19,7 @@ Required Properties: - "samsung,exynos5260-pinctrl": for Exynos5260 compatible pin-controller. - "samsung,exynos5410-pinctrl": for Exynos5410 compatible pin-controller. - "samsung,exynos5420-pinctrl": for Exynos5420 compatible pin-controller. + - "samsung,exynos5433-pinctrl": for Exynos5433 compatible pin-controller. - "samsung,exynos7-pinctrl": for Exynos7 compatible pin-controller. - reg: Base address of the pin controller hardware module and length of diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c index 051b5bf701a8..4f95983e0cdd 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c @@ -1350,6 +1350,11 @@ static const struct samsung_pin_bank_data exynos5433_pin_banks0[] = { EXYNOS_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04), EXYNOS_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08), EXYNOS_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c), + EXYNOS_PIN_BANK_EINTW_EXT(8, 0x020, "gpf1", 0x1004), + EXYNOS_PIN_BANK_EINTW_EXT(4, 0x040, "gpf2", 0x1008), + EXYNOS_PIN_BANK_EINTW_EXT(4, 0x060, "gpf3", 0x100c), + EXYNOS_PIN_BANK_EINTW_EXT(8, 0x080, "gpf4", 0x1010), + EXYNOS_PIN_BANK_EINTW_EXT(8, 0x0a0, "gpf5", 0x1014), }; /* pin banks of exynos5433 pin-controller - AUD */ diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h b/drivers/pinctrl/samsung/pinctrl-exynos.h index 0f0f7cedb2dc..4b737b6c434d 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos.h +++ b/drivers/pinctrl/samsung/pinctrl-exynos.h @@ -79,6 +79,17 @@ .name = id \ } +#define EXYNOS_PIN_BANK_EINTW_EXT(pins, reg, id, offs) \ + { \ + .type = &bank_type_off, \ + .pctl_offset = reg, \ + .nr_pins = pins, \ + .eint_type = EINT_TYPE_WKUP, \ + .eint_offset = offs, \ + .eint_ext = true, \ + .name = id \ + } + /** * struct exynos_weint_data: irq specific data for all the wakeup interrupts * generated by the external wakeup interrupt controller. diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c index 513fe6b23248..57e22085c2db 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.c +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c @@ -338,6 +338,7 @@ static void pin_to_reg_bank(struct samsung_pinctrl_drv_data *drvdata, struct samsung_pin_bank **bank) { struct samsung_pin_bank *b; + void __iomem *virt_base = drvdata->virt_base; b = drvdata->pin_banks; @@ -345,7 +346,10 @@ static void pin_to_reg_bank(struct samsung_pinctrl_drv_data *drvdata, ((b->pin_base + b->nr_pins - 1) < pin)) b++; - *reg = drvdata->virt_base + b->pctl_offset; + if (b->eint_ext) + virt_base = drvdata->ext_base; + + *reg = virt_base + b->pctl_offset; *offset = pin - b->pin_base; if (bank) *bank = b; @@ -523,10 +527,12 @@ static void samsung_gpio_set_value(struct gpio_chip *gc, { struct samsung_pin_bank *bank = gpiochip_get_data(gc); const struct samsung_pin_bank_type *type = bank->type; + void __iomem *virt_base = bank->eint_ext ? + bank->drvdata->ext_base : bank->drvdata->virt_base; void __iomem *reg; u32 data; - reg = bank->drvdata->virt_base + bank->pctl_offset; + reg = virt_base + bank->pctl_offset; data = readl(reg + type->reg_offset[PINCFG_TYPE_DAT]); data &= ~(1 << offset); @@ -553,8 +559,10 @@ static int samsung_gpio_get(struct gpio_chip *gc, unsigned offset) u32 data; struct samsung_pin_bank *bank = gpiochip_get_data(gc); const struct samsung_pin_bank_type *type = bank->type; + void __iomem *virt_base = bank->eint_ext ? + bank->drvdata->ext_base : bank->drvdata->virt_base; - reg = bank->drvdata->virt_base + bank->pctl_offset; + reg = virt_base + bank->pctl_offset; data = readl(reg + type->reg_offset[PINCFG_TYPE_DAT]); data >>= offset; @@ -574,6 +582,7 @@ static int samsung_gpio_set_direction(struct gpio_chip *gc, const struct samsung_pin_bank_type *type; struct samsung_pin_bank *bank; struct samsung_pinctrl_drv_data *drvdata; + void __iomem *virt_base; void __iomem *reg; u32 data, mask, shift; @@ -581,7 +590,8 @@ static int samsung_gpio_set_direction(struct gpio_chip *gc, type = bank->type; drvdata = bank->drvdata; - reg = drvdata->virt_base + bank->pctl_offset + + virt_base = bank->eint_ext ? drvdata->ext_base : drvdata->virt_base; + reg = virt_base + bank->pctl_offset + type->reg_offset[PINCFG_TYPE_FUNC]; mask = (1 << type->fld_width[PINCFG_TYPE_FUNC]) - 1; @@ -1007,6 +1017,7 @@ samsung_pinctrl_get_soc_data(struct samsung_pinctrl_drv_data *d, bank->eint_type = bdata->eint_type; bank->eint_mask = bdata->eint_mask; bank->eint_offset = bdata->eint_offset; + bank->eint_ext = bdata->eint_ext; bank->name = bdata->name; spin_lock_init(&bank->slock); @@ -1065,6 +1076,14 @@ static int samsung_pinctrl_probe(struct platform_device *pdev) if (IS_ERR(drvdata->virt_base)) return PTR_ERR(drvdata->virt_base); + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (res) { + drvdata->ext_base = + devm_ioremap(dev, res->start, resource_size(res)); + if (!drvdata->ext_base) + return -ENXIO; + } + res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); if (res) drvdata->irq = res->start; @@ -1102,16 +1121,20 @@ static int samsung_pinctrl_probe(struct platform_device *pdev) static void samsung_pinctrl_suspend_dev( struct samsung_pinctrl_drv_data *drvdata) { - void __iomem *virt_base = drvdata->virt_base; + void __iomem *virt_base; int i; for (i = 0; i < drvdata->nr_banks; i++) { struct samsung_pin_bank *bank = &drvdata->pin_banks[i]; - void __iomem *reg = virt_base + bank->pctl_offset; + void __iomem *reg; const u8 *offs = bank->type->reg_offset; const u8 *widths = bank->type->fld_width; enum pincfg_type type; + virt_base = bank->eint_ext ? + drvdata->ext_base : drvdata->virt_base; + reg = virt_base + bank->pctl_offset; + /* Registers without a powerdown config aren't lost */ if (!widths[PINCFG_TYPE_CON_PDN]) continue; @@ -1148,7 +1171,7 @@ static void samsung_pinctrl_suspend_dev( */ static void samsung_pinctrl_resume_dev(struct samsung_pinctrl_drv_data *drvdata) { - void __iomem *virt_base = drvdata->virt_base; + void __iomem *virt_base; int i; if (drvdata->resume) @@ -1156,11 +1179,15 @@ static void samsung_pinctrl_resume_dev(struct samsung_pinctrl_drv_data *drvdata) for (i = 0; i < drvdata->nr_banks; i++) { struct samsung_pin_bank *bank = &drvdata->pin_banks[i]; - void __iomem *reg = virt_base + bank->pctl_offset; + void __iomem *reg; const u8 *offs = bank->type->reg_offset; const u8 *widths = bank->type->fld_width; enum pincfg_type type; + virt_base = bank->eint_ext ? + drvdata->ext_base : drvdata->virt_base; + reg = virt_base + bank->pctl_offset; + /* Registers without a powerdown config aren't lost */ if (!widths[PINCFG_TYPE_CON_PDN]) continue; diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h index cd31bfaf62cb..3005135f4565 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.h +++ b/drivers/pinctrl/samsung/pinctrl-samsung.h @@ -131,6 +131,7 @@ struct samsung_pin_bank_data { enum eint_type eint_type; u32 eint_mask; u32 eint_offset; + bool eint_ext; const char *name; }; @@ -163,6 +164,7 @@ struct samsung_pin_bank { enum eint_type eint_type; u32 eint_mask; u32 eint_offset; + bool eint_ext; const char *name; u32 pin_base; @@ -201,6 +203,8 @@ struct samsung_pin_ctrl { * struct samsung_pinctrl_drv_data: wrapper for holding driver data together. * @node: global list node * @virt_base: register base address of the controller. + * @ext_base: external register base address of the controller. + * @ext_base: external register base address of the controller. * @dev: device instance representing the controller. * @irq: interrpt number used by the controller to notify gpio interrupts. * @ctrl: pin controller instance managed by the driver. @@ -216,6 +220,7 @@ struct samsung_pin_ctrl { struct samsung_pinctrl_drv_data { struct list_head node; void __iomem *virt_base; + void __iomem *ext_base; struct device *dev; int irq;