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[37.209.75.7]) by smtp.googlemail.com with ESMTPSA id bc10sm30663679wjc.32.2016.08.17.02.25.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 17 Aug 2016 02:25:32 -0700 (PDT) Message-ID: <1471425931.1934.18.camel@googlemail.com> Subject: [PATCH] ARM: dts: imx6sx: document SION necessity of ENET1_REF_CLK1 From: Christoph Fritz To: Shawn Guo , Fabio Estevam Date: Wed, 17 Aug 2016 11:25:31 +0200 In-Reply-To: <20160815052244.mwygjlo72e46w353@pengutronix.de> References: <1458825865-7434-1-git-send-email-u.kleine-koenig@pengutronix.de> <1458825865-7434-7-git-send-email-u.kleine-koenig@pengutronix.de> <1470350663.26773.41.camel@googlemail.com> <20160805065845.GI17874@pengutronix.de> <1470398615.1936.22.camel@googlemail.com> <1471120532.1923.4.camel@googlemail.com> <20160815052244.mwygjlo72e46w353@pengutronix.de> X-Mailer: Evolution 3.12.9-1+b1 Mime-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160817_022557_235417_69356691 X-CRM114-Status: GOOD ( 10.38 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: chf.fritz@googlemail.com Cc: Martin Fuzzey , Baruch Siach , "linux-serial@vger.kernel.org" , Greg Kroah-Hartman , kernel@pengutronix.de, Uwe =?ISO-8859-1?Q?Kleine-K=F6nig?= , linux-arm-kernel Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Christoph Fritz --- arch/arm/boot/dts/imx6sx-pinfunc.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/imx6sx-pinfunc.h b/arch/arm/boot/dts/imx6sx-pinfunc.h index bb9c6b7..42c4c80 100644 --- a/arch/arm/boot/dts/imx6sx-pinfunc.h +++ b/arch/arm/boot/dts/imx6sx-pinfunc.h @@ -308,6 +308,20 @@ #define MX6SX_PAD_ENET1_RX_CLK__VDEC_DEBUG_35 0x008C 0x03D4 0x0000 0x8 0x0 #define MX6SX_PAD_ENET1_RX_CLK__PCIE_CTRL_DEBUG_29 0x008C 0x03D4 0x0000 0x9 0x0 #define MX6SX_PAD_ENET1_TX_CLK__ENET1_TX_CLK 0x0090 0x03D8 0x0000 0x0 0x0 +/* + * SION bit is necessary for ENET1_REF_CLK1 (ENET2_REF_CLK2 untested) if it is + * used as clock output of IMX6SX_CLK_ENET_REF (ENET1_TX_CLK) to e.g. supply a + * PHY in RMII mode. This configuration is valid if: + * - bit 1 in field IMX6SX_GPR1_FEC_CLOCK_PAD_DIR_MASK is set + * - bit 1 in field IMX6SX_GPR1_FEC_CLOCK_MUX_SEL_MASK unset + * It seems to be a silicon bug that in this configuration ENET1_TX reference + * clock isn't provided automatically. According to i.MX6SX reference manual + * (IOMUXC_GPR_GPR1 field descriptions: ENET1_CLK_SEL, Rev. 0 from 2/2015) it + * should be the case. + * So this might have unwanted side effects for other hardware units that are + * also connected to that pin and using respective function as input (e.g. + * UART1's DTR handling on MX6SX_PAD_ENET1_TX_CLK__UART1_DTR_B). + */ #define MX6SX_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x0090 0x03D8 0x0760 0x1 0x1 #define MX6SX_PAD_ENET1_TX_CLK__AUDMUX_AUD4_RXD 0x0090 0x03D8 0x0644 0x2 0x1 #define MX6SX_PAD_ENET1_TX_CLK__UART1_DTR_B 0x0090 0x03D8 0x0000 0x3 0x0