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Thu, 25 Aug 2016 15:57:24 +0900 (KST) Received: from chan.10.32.193.11 ([10.113.62.212]) by mmp1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0OCG007BZDZNHZ00@mmp1.samsung.com>; Thu, 25 Aug 2016 15:57:23 +0900 (KST) From: Chanwoo Choi To: s.nawrocki@samsung.com, tomasz.figa@gmail.com Subject: [PATCH v2 1/3] dt-bindings: Add the clock id for CMU_CDREX (DRAM Express Controller) Date: Thu, 25 Aug 2016 15:57:16 +0900 Message-id: <1472108238-24309-2-git-send-email-cw00.choi@samsung.com> X-Mailer: git-send-email 1.8.0 In-reply-to: <1472108238-24309-1-git-send-email-cw00.choi@samsung.com> References: <1472108238-24309-1-git-send-email-cw00.choi@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrNLMWRmVeSWpSXmKPExsWyRsSkUPfKtH3hBnsesFtMvHGFxeL6l+es Fq9fGFr0P37NbLHp8TVWi48991gtLu+aw2Yx4/w+JouLp1wtDr9pZ7X4caabxWLVrj+MDjwe 72+0sntc7utl8tg56y67x6ZVnWwem5fUe/RtWcXo8XmTXAB7FJdNSmpOZllqkb5dAlfGo3cP mQv2cVXs/LeQsYHxM0cXIyeHhICJxIOHa1khbDGJC/fWs3UxcnEICaxglDj1+DArTFHDoTnM EImljBKPX7ezQDhfGCVe9H1iBqliE9CS2P/iBlA7B4eIgKHEzUNKIGFmgQVMEh2b2EFsYYF4 iY3Xv4LZLAKqEn+PzQZr5RVwlTj1/hobxDI5iQ97HoHVcAq4SUyZs4AJxBYCqlny/TojyF4J gVPsEicXf2SEGCQg8W3yIRaQvRICshKbDjBDzJGUOLjiBssERuEFjAyrGEVTC5ILipPSi4z0 ihNzi0vz0vWS83M3MQLj5PS/Z307GG8esD7EKMDBqMTDu2PV3nAh1sSy4srcQ4ymQBsmMkuJ JucDozGvJN7Q2MzIwtTE1NjI3NJMSZw3QepnsJBAemJJanZqakFqUXxRaU5q8SFGJg5OqQZG mY1unq2SLezxDonVT3kkOKI922c4fTWZcdX4dnzZvZsdYud2ZUxW4V365s4u1XUPHi/vPFlx 7WUEs9SXntnHEgu1G11/LlmxLqA2y3Sx49t449LaDQdiHx737fi17RcXk9LZzIrX+Uvjue6e Mcr58WUKm9hjGTb7lH3e/SaC3g82MfsaJS1RYinOSDTUYi4qTgQAR/kbmY4CAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrBIsWRmVeSWpSXmKPExsVy+t9jAd0r0/aFG3TNYrKYeOMKi8X1L89Z LV6/MLTof/ya2WLT42usFh977rFaXN41h81ixvl9TBYXT7laHH7Tzmrx40w3i8WqXX8YHXg8 3t9oZfe43NfL5LFz1l12j02rOtk8Ni+p9+jbsorR4/MmuQD2qAZGm4zUxJTUIoXUvOT8lMy8 dFsl7+B453hTMwNDXUNLC3MlhbzE3FRbJRefAF23zBygO5UUyhJzSoFCAYnFxUr6dpgmhIa4 6VrANEbo+oYEwfUYGaCBhDWMGY/ePWQu2MdVsfPfQsYGxs8cXYycHBICJhINh+YwQ9hiEhfu rWfrYuTiEBJYyijx+HU7C4TzhVHiRd8nsCo2AS2J/S9uAFVxcIgIGErcPKQEEmYWWMAk0bGJ HcQWFoiX2Hj9K5jNIqAq8ffYbLBWXgFXiVPvr7FBLJOT+LDnEVgNp4CbxJQ5C5hAbCGgmiXf rzNOYORdwMiwilEitSC5oDgpPdcwL7Vcrzgxt7g0L10vOT93EyM4Fp9J7WA8uMv9EKMAB6MS D6+ByL5wIdbEsuLK3EOMEhzMSiK8hyYDhXhTEiurUovy44tKc1KLDzGaAh02kVlKNDkfmCby SuINjU3MjCyNzA0tjIzNlcR5H/9fFyYkkJ5YkpqdmlqQWgTTx8TBKdXAuN9mxtUrynUcYXet 3ki+evH68g67JwxCwp38Sc4ZX6+6i6z6kaLjq7H/fO7uqF3nEz6fC2kPqZSznBHLtDVFwGhJ cd+T6ZdVlj3q08njLPCRM006ct868ZyGUe+bng2G0ZM6+blvmk7cVH79rZLRDm7xJQ/bpVIF pS/qTIvJOHV3Qt78g7OnK7EUZyQaajEXFScCAPQmWabbAgAA DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160824_235747_169184_502CC3E6 X-CRM114-Status: GOOD ( 10.09 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: k.kozlowski@samsung.com, linux-samsung-soc@vger.kernel.org, mturquette@baylibre.com, sboyd@codeaurora.org, linux-kernel@vger.kernel.org, Chanwoo Choi , kgene@kernel.org, chanwoo@kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds the new clock id for CMU_CDRES (DRAM Express Controller) geneates the clocks for DRAM and NoC (Network on Chip) bus clock. Signed-off-by: Chanwoo Choi --- include/dt-bindings/clock/exynos5420.h | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h index 17ab8394bec7..6fd21c291416 100644 --- a/include/dt-bindings/clock/exynos5420.h +++ b/include/dt-bindings/clock/exynos5420.h @@ -214,6 +214,9 @@ #define CLK_MOUT_SW_ACLK400 651 #define CLK_MOUT_USER_ACLK300_GSCL 652 #define CLK_MOUT_SW_ACLK300_GSCL 653 +#define CLK_MOUT_MCLK_CDREX 654 +#define CLK_MOUT_BPLL 655 +#define CLK_MOUT_MX_MSPLL_CCORE 656 /* divider clocks */ #define CLK_DOUT_PIXEL 768 @@ -239,8 +242,14 @@ #define CLK_DOUT_ACLK300_DISP1 788 #define CLK_DOUT_ACLK300_GSCL 789 #define CLK_DOUT_ACLK400_DISP1 790 +#define CLK_DOUT_PCLK_CDREX 791 +#define CLK_DOUT_SCLK_CDREX 792 +#define CLK_DOUT_ACLK_CDREX1 793 +#define CLK_DOUT_CCLK_DREX0 794 +#define CLK_DOUT_CLK2X_PHY0 795 +#define CLK_DOUT_PCLK_CORE_MEM 796 /* must be greater than maximal clock id */ -#define CLK_NR_CLKS 791 +#define CLK_NR_CLKS 797 #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */