From patchwork Thu Aug 25 17:50:11 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Olliver Schinagl X-Patchwork-Id: 9299641 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id D14F060757 for ; Thu, 25 Aug 2016 17:53:02 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C722E293AD for ; Thu, 25 Aug 2016 17:53:02 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id BC13C293B3; Thu, 25 Aug 2016 17:53:02 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED, T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 3D6D4293AE for ; Thu, 25 Aug 2016 17:53:02 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.85_2 #1 (Red Hat Linux)) id 1bcyob-00055u-7X; Thu, 25 Aug 2016 17:51:45 +0000 Received: from 7of9.schinagl.nl ([88.159.158.68]) by bombadil.infradead.org with esmtps (Exim 4.85_2 #1 (Red Hat Linux)) id 1bcyni-0004lM-5b for linux-arm-kernel@lists.infradead.org; Thu, 25 Aug 2016 17:50:52 +0000 Received: from um-mbp-306.ultimaker.com (unknown [92.69.209.117]) by 7of9.schinagl.nl (Postfix) with ESMTPA id B2C4039A938; Thu, 25 Aug 2016 19:50:28 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=schinagl.nl; s=7of9; t=1472147429; bh=8OJoWXiYcICVTHIPVwmV734VZYP3dHw5zKujac2ZETU=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=U40b4SpLTs+SL3bp63E29FAa0td378NN3J3x6buE6iOH2zWF5P5rypnojkIm59MPd kfZkuQEWgirtplWnVTYMIvkOMokGK+IJl+Dk57XxpzSjOdc21qyfFWledV6zF6gsfX IQweUPZ6pnq8Sa0VcGMRfv5pQYnTsLNa5KBJE5tw= From: Olliver Schinagl To: Alexandre Belloni , Thierry Reding , Maxime Ripard , Chen-Yu Tsai Subject: [PATCH 2/2] pwm: sunxi: Yield some time to the pwm-block to become ready Date: Thu, 25 Aug 2016 19:50:11 +0200 Message-Id: <1472147411-30424-3-git-send-email-oliver@schinagl.nl> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1472147411-30424-1-git-send-email-oliver@schinagl.nl> References: <1472147411-30424-1-git-send-email-oliver@schinagl.nl> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160825_105050_686068_19BD37D5 X-CRM114-Status: GOOD ( 13.48 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Olliver Schinagl MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Olliver Schinagl The pwm-block of some of the sunxi chips feature a 'ready' flag to indicate the software that it is ready for new commands. Right now, when we call pwm_config and set the period, we write the values to the registers, and turn off the clock to the IP. Because of this, the hardware does not have time to configure the hardware and set the 'ready' flag. By running the clock just before making new changes and before checking if the hardware is ready, the hardware has time to reconfigure itself and set the clear the flag appropriately. Signed-off-by: Olliver Schinagl --- drivers/pwm/pwm-sun4i.c | 43 +++++++++++++++++++++++++------------------ 1 file changed, 25 insertions(+), 18 deletions(-) diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c index 5e97c8a..dd198c3 100644 --- a/drivers/pwm/pwm-sun4i.c +++ b/drivers/pwm/pwm-sun4i.c @@ -105,6 +105,22 @@ static int sun4i_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, u64 clk_rate, div = 0; unsigned int prescaler = 0; int err; + int ret = 0; + + /* Let the PWM hardware run before making any changes. We do this to + * allow the hardware to have some time to clear the 'ready' flag. + */ + err = clk_prepare_enable(sun4i_pwm->clk); + if (err) { + dev_err(chip->dev, "failed to enable PWM clock\n"); + return err; + } + spin_lock(&sun4i_pwm->ctrl_lock); + val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG); + clk_gate = val & BIT_CH(PWM_CLK_GATING, pwm->hwpwm); + val |= BIT_CH(PWM_CLK_GATING, pwm->hwpwm); + sun4i_pwm_writel(sun4i_pwm, val, PWM_CTRL_REG); + spin_unlock(&sun4i_pwm->ctrl_lock); clk_rate = clk_get_rate(sun4i_pwm->clk); @@ -137,7 +153,9 @@ static int sun4i_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, if (div - 1 > PWM_PRD_MASK) { dev_err(chip->dev, "period exceeds the maximum value\n"); - return -EINVAL; + ret = -EINVAL; + spin_lock(&sun4i_pwm->ctrl_lock); + goto out; } } @@ -146,26 +164,14 @@ static int sun4i_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, do_div(div, period_ns); dty = div; - err = clk_prepare_enable(sun4i_pwm->clk); - if (err) { - dev_err(chip->dev, "failed to enable PWM clock\n"); - return err; - } - spin_lock(&sun4i_pwm->ctrl_lock); val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG); - if (sun4i_pwm->data->has_rdy && (val & PWM_RDY(pwm->hwpwm))) { - spin_unlock(&sun4i_pwm->ctrl_lock); - clk_disable_unprepare(sun4i_pwm->clk); - return -EBUSY; - } - - clk_gate = val & BIT_CH(PWM_CLK_GATING, pwm->hwpwm); - if (clk_gate) { - val &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm); - sun4i_pwm_writel(sun4i_pwm, val, PWM_CTRL_REG); + ret = -EBUSY; + goto out; } + val &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm); + sun4i_pwm_writel(sun4i_pwm, val, PWM_CTRL_REG); val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG); val &= ~BIT_CH(PWM_PRESCAL_MASK, pwm->hwpwm); @@ -175,6 +181,7 @@ static int sun4i_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, val = (dty & PWM_DTY_MASK) | PWM_PRD(prd); sun4i_pwm_writel(sun4i_pwm, val, PWM_CH_PRD(pwm->hwpwm)); +out: if (clk_gate) { val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG); val |= clk_gate; @@ -184,7 +191,7 @@ static int sun4i_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, spin_unlock(&sun4i_pwm->ctrl_lock); clk_disable_unprepare(sun4i_pwm->clk); - return 0; + return ret; } static int sun4i_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm,